📄 vga.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key register register VGAsingl:inst\|MMD\[0\] VGAsingl:inst\|MMD\[1\] 360.1 MHz Internal " "Info: Clock \"key\" Internal fmax is restricted to 360.1 MHz between source register \"VGAsingl:inst\|MMD\[0\]\" and destination register \"VGAsingl:inst\|MMD\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.236 ns + Longest register register " "Info: + Longest register to register delay is 1.236 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|MMD\[0\] 1 REG LCFF_X26_Y4_N21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y4_N21; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|MMD[0] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.647 ns) 1.128 ns rtl~1 2 COMB LCCOMB_X26_Y4_N28 1 " "Info: 2: + IC(0.481 ns) + CELL(0.647 ns) = 1.128 ns; Loc. = LCCOMB_X26_Y4_N28; Fanout = 1; COMB Node = 'rtl~1'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.128 ns" { VGAsingl:inst|MMD[0] rtl~1 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.236 ns VGAsingl:inst\|MMD\[1\] 3 REG LCFF_X26_Y4_N29 5 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.236 ns; Loc. = LCFF_X26_Y4_N29; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.108 ns" { rtl~1 VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.755 ns ( 61.08 % ) " "Info: Total cell delay = 0.755 ns ( 61.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.481 ns ( 38.92 % ) " "Info: Total interconnect delay = 0.481 ns ( 38.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.236 ns" { VGAsingl:inst|MMD[0] rtl~1 VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.236 ns" { VGAsingl:inst|MMD[0] rtl~1 VGAsingl:inst|MMD[1] } { 0.000ns 0.481ns 0.000ns } { 0.000ns 0.647ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key destination 7.384 ns + Shortest register " "Info: + Shortest clock path from clock \"key\" to destination register is 7.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns key 1 CLK PIN_103 5 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_103; Fanout = 5; CLK Node = 'key'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { key } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 144 -16 152 160 "key" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.714 ns) + CELL(0.666 ns) 7.384 ns VGAsingl:inst\|MMD\[1\] 2 REG LCFF_X26_Y4_N29 5 " "Info: 2: + IC(5.714 ns) + CELL(0.666 ns) = 7.384 ns; Loc. = LCFF_X26_Y4_N29; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "6.380 ns" { key VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.670 ns ( 22.62 % ) " "Info: Total cell delay = 1.670 ns ( 22.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.714 ns ( 77.38 % ) " "Info: Total interconnect delay = 5.714 ns ( 77.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "7.384 ns" { key VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.384 ns" { key key~combout VGAsingl:inst|MMD[1] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.004ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key source 7.384 ns - Longest register " "Info: - Longest clock path from clock \"key\" to source register is 7.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns key 1 CLK PIN_103 5 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_103; Fanout = 5; CLK Node = 'key'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { key } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 144 -16 152 160 "key" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.714 ns) + CELL(0.666 ns) 7.384 ns VGAsingl:inst\|MMD\[0\] 2 REG LCFF_X26_Y4_N21 5 " "Info: 2: + IC(5.714 ns) + CELL(0.666 ns) = 7.384 ns; Loc. = LCFF_X26_Y4_N21; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "6.380 ns" { key VGAsingl:inst|MMD[0] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.670 ns ( 22.62 % ) " "Info: Total cell delay = 1.670 ns ( 22.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.714 ns ( 77.38 % ) " "Info: Total interconnect delay = 5.714 ns ( 77.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "7.384 ns" { key VGAsingl:inst|MMD[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.384 ns" { key key~combout VGAsingl:inst|MMD[0] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.004ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "7.384 ns" { key VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.384 ns" { key key~combout VGAsingl:inst|MMD[1] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.004ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "7.384 ns" { key VGAsingl:inst|MMD[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.384 ns" { key key~combout VGAsingl:inst|MMD[0] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.004ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.236 ns" { VGAsingl:inst|MMD[0] rtl~1 VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.236 ns" { VGAsingl:inst|MMD[0] rtl~1 VGAsingl:inst|MMD[1] } { 0.000ns 0.481ns 0.000ns } { 0.000ns 0.647ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "7.384 ns" { key VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.384 ns" { key key~combout VGAsingl:inst|MMD[1] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.004ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "7.384 ns" { key VGAsingl:inst|MMD[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.384 ns" { key key~combout VGAsingl:inst|MMD[0] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.004ns 0.666ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { VGAsingl:inst|MMD[1] } { } { } } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 23 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk r VGAsingl:inst\|LL\[6\] 20.035 ns register " "Info: tco from clock \"clk\" to destination pin \"r\" through register \"VGAsingl:inst\|LL\[6\]\" is 20.035 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.440 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { clk } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.970 ns) 3.065 ns VGAsingl:inst\|FS\[5\] 3 REG LCFF_X1_Y6_N27 3 " "Info: 3: + IC(0.812 ns) + CELL(0.970 ns) = 3.065 ns; Loc. = LCFF_X1_Y6_N27; Fanout = 3; REG Node = 'VGAsingl:inst\|FS\[5\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.782 ns" { clk~clkctrl VGAsingl:inst|FS[5] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.000 ns) 3.891 ns VGAsingl:inst\|FS\[5\]~clkctrl 4 COMB CLKCTRL_G1 5 " "Info: 4: + IC(0.826 ns) + CELL(0.000 ns) = 3.891 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'VGAsingl:inst\|FS\[5\]~clkctrl'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.826 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.843 ns) + CELL(0.970 ns) 5.704 ns VGAsingl:inst\|CC\[4\] 5 REG LCFF_X27_Y4_N11 7 " "Info: 5: + IC(0.843 ns) + CELL(0.970 ns) = 5.704 ns; Loc. = LCFF_X27_Y4_N11; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.813 ns" { VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 6.922 ns VGAsingl:inst\|CC\[4\]~clkctrl 6 COMB CLKCTRL_G6 9 " "Info: 6: + IC(1.218 ns) + CELL(0.000 ns) = 6.922 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst\|CC\[4\]~clkctrl'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.218 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 8.440 ns VGAsingl:inst\|LL\[6\] 7 REG LCFF_X24_Y2_N25 9 " "Info: 7: + IC(0.852 ns) + CELL(0.666 ns) = 8.440 ns; Loc. = LCFF_X24_Y2_N25; Fanout = 9; REG Node = 'VGAsingl:inst\|LL\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.518 ns" { VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[6] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 44.38 % ) " "Info: Total cell delay = 3.746 ns ( 44.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.694 ns ( 55.62 % ) " "Info: Total interconnect delay = 4.694 ns ( 55.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[6] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.291 ns + Longest register pin " "Info: + Longest register to pin delay is 11.291 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|LL\[6\] 1 REG LCFF_X24_Y2_N25 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y2_N25; Fanout = 9; REG Node = 'VGAsingl:inst\|LL\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|LL[6] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.614 ns) 1.834 ns VGAsingl:inst\|GRBY\[2\]~813 2 COMB LCCOMB_X24_Y3_N18 2 " "Info: 2: + IC(1.220 ns) + CELL(0.614 ns) = 1.834 ns; Loc. = LCCOMB_X24_Y3_N18; Fanout = 2; COMB Node = 'VGAsingl:inst\|GRBY\[2\]~813'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.834 ns" { VGAsingl:inst|LL[6] VGAsingl:inst|GRBY[2]~813 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.616 ns) 2.834 ns VGAsingl:inst\|GRBY\[2\]~815 3 COMB LCCOMB_X24_Y3_N2 1 " "Info: 3: + IC(0.384 ns) + CELL(0.616 ns) = 2.834 ns; Loc. = LCCOMB_X24_Y3_N2; Fanout = 1; COMB Node = 'VGAsingl:inst\|GRBY\[2\]~815'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.000 ns" { VGAsingl:inst|GRBY[2]~813 VGAsingl:inst|GRBY[2]~815 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.624 ns) 3.834 ns VGAsingl:inst\|GRBY\[2\]~817 4 COMB LCCOMB_X24_Y3_N10 1 " "Info: 4: + IC(0.376 ns) + CELL(0.624 ns) = 3.834 ns; Loc. = LCCOMB_X24_Y3_N10; Fanout = 1; COMB Node = 'VGAsingl:inst\|GRBY\[2\]~817'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.000 ns" { VGAsingl:inst|GRBY[2]~815 VGAsingl:inst|GRBY[2]~817 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.427 ns) + CELL(0.651 ns) 5.912 ns VGAsingl:inst\|GRBP\[2\]~752 5 COMB LCCOMB_X26_Y4_N0 1 " "Info: 5: + IC(1.427 ns) + CELL(0.651 ns) = 5.912 ns; Loc. = LCCOMB_X26_Y4_N0; Fanout = 1; COMB Node = 'VGAsingl:inst\|GRBP\[2\]~752'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "2.078 ns" { VGAsingl:inst|GRBY[2]~817 VGAsingl:inst|GRBP[2]~752 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.615 ns) 6.891 ns VGAsingl:inst\|R 6 COMB LCCOMB_X26_Y4_N16 1 " "Info: 6: + IC(0.364 ns) + CELL(0.615 ns) = 6.891 ns; Loc. = LCCOMB_X26_Y4_N16; Fanout = 1; COMB Node = 'VGAsingl:inst\|R'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.979 ns" { VGAsingl:inst|GRBP[2]~752 VGAsingl:inst|R } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.284 ns) + CELL(3.116 ns) 11.291 ns r 7 PIN PIN_107 0 " "Info: 7: + IC(1.284 ns) + CELL(3.116 ns) = 11.291 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'r'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "4.400 ns" { VGAsingl:inst|R r } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 160 464 640 176 "r" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.236 ns ( 55.23 % ) " "Info: Total cell delay = 6.236 ns ( 55.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.055 ns ( 44.77 % ) " "Info: Total interconnect delay = 5.055 ns ( 44.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "11.291 ns" { VGAsingl:inst|LL[6] VGAsingl:inst|GRBY[2]~813 VGAsingl:inst|GRBY[2]~815 VGAsingl:inst|GRBY[2]~817 VGAsingl:inst|GRBP[2]~752 VGAsingl:inst|R r } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.291 ns" { VGAsingl:inst|LL[6] VGAsingl:inst|GRBY[2]~813 VGAsingl:inst|GRBY[2]~815 VGAsingl:inst|GRBY[2]~817 VGAsingl:inst|GRBP[2]~752 VGAsingl:inst|R r } { 0.000ns 1.220ns 0.384ns 0.376ns 1.427ns 0.364ns 1.284ns } { 0.000ns 0.614ns 0.616ns 0.624ns 0.651ns 0.615ns 3.116ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[6] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "11.291 ns" { VGAsingl:inst|LL[6] VGAsingl:inst|GRBY[2]~813 VGAsingl:inst|GRBY[2]~815 VGAsingl:inst|GRBY[2]~817 VGAsingl:inst|GRBP[2]~752 VGAsingl:inst|R r } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.291 ns" { VGAsingl:inst|LL[6] VGAsingl:inst|GRBY[2]~813 VGAsingl:inst|GRBY[2]~815 VGAsingl:inst|GRBY[2]~817 VGAsingl:inst|GRBP[2]~752 VGAsingl:inst|R r } { 0.000ns 1.220ns 0.384ns 0.376ns 1.427ns 0.364ns 1.284ns } { 0.000ns 0.614ns 0.616ns 0.624ns 0.651ns 0.615ns 3.116ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key b 11.941 ns Longest " "Info: Longest tpd from source pin \"key\" to destination pin \"b\" is 11.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns key 1 CLK PIN_103 5 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_103; Fanout = 5; CLK Node = 'key'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { key } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 144 -16 152 160 "key" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.793 ns) + CELL(0.647 ns) 7.444 ns VGAsingl:inst\|B 2 COMB LCCOMB_X26_Y4_N24 1 " "Info: 2: + IC(5.793 ns) + CELL(0.647 ns) = 7.444 ns; Loc. = LCCOMB_X26_Y4_N24; Fanout = 1; COMB Node = 'VGAsingl:inst\|B'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "6.440 ns" { key VGAsingl:inst|B } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(3.116 ns) 11.941 ns b 3 PIN PIN_105 0 " "Info: 3: + IC(1.381 ns) + CELL(3.116 ns) = 11.941 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'b'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "4.497 ns" { VGAsingl:inst|B b } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 192 472 648 208 "b" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.767 ns ( 39.92 % ) " "Info: Total cell delay = 4.767 ns ( 39.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.174 ns ( 60.08 % ) " "Info: Total interconnect delay = 7.174 ns ( 60.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "11.941 ns" { key VGAsingl:inst|B b } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.941 ns" { key key~combout VGAsingl:inst|B b } { 0.000ns 0.000ns 5.793ns 1.381ns } { 0.000ns 1.004ns 0.647ns 3.116ns } } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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