vga.tan.qmsg

FPGA EP2C5 VGA 使用verilogHdl

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key " "Info: Assuming node \"key\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 144 -16 152 160 "key" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "key" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst\|FS\[5\] " "Info: Detected ripple clock \"VGAsingl:inst\|FS\[5\]\" as buffer" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|FS\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst\|CC\[4\] " "Info: Detected ripple clock \"VGAsingl:inst\|CC\[4\]\" as buffer" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|CC\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VGAsingl:inst\|LL\[3\] register VGAsingl:inst\|LL\[7\] 254.91 MHz 3.923 ns Internal " "Info: Clock \"clk\" has Internal fmax of 254.91 MHz between source register \"VGAsingl:inst\|LL\[3\]\" and destination register \"VGAsingl:inst\|LL\[7\]\" (period= 3.923 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.659 ns + Longest register register " "Info: + Longest register to register delay is 3.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|LL\[3\] 1 REG LCFF_X24_Y2_N11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y2_N11; Fanout = 7; REG Node = 'VGAsingl:inst\|LL\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|LL[3] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.747 ns) + CELL(0.596 ns) 1.343 ns VGAsingl:inst\|add~336 2 COMB LCCOMB_X24_Y2_N10 2 " "Info: 2: + IC(0.747 ns) + CELL(0.596 ns) = 1.343 ns; Loc. = LCCOMB_X24_Y2_N10; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~336'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.343 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|add~336 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.429 ns VGAsingl:inst\|add~338 3 COMB LCCOMB_X24_Y2_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.429 ns; Loc. = LCCOMB_X24_Y2_N12; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~338'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.086 ns" { VGAsingl:inst|add~336 VGAsingl:inst|add~338 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.619 ns VGAsingl:inst\|add~340 4 COMB LCCOMB_X24_Y2_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.190 ns) = 1.619 ns; Loc. = LCCOMB_X24_Y2_N14; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.190 ns" { VGAsingl:inst|add~338 VGAsingl:inst|add~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.705 ns VGAsingl:inst\|add~342 5 COMB LCCOMB_X24_Y2_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.705 ns; Loc. = LCCOMB_X24_Y2_N16; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~342'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.086 ns" { VGAsingl:inst|add~340 VGAsingl:inst|add~342 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.211 ns VGAsingl:inst\|add~343 6 COMB LCCOMB_X24_Y2_N18 1 " "Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 2.211 ns; Loc. = LCCOMB_X24_Y2_N18; Fanout = 1; COMB Node = 'VGAsingl:inst\|add~343'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.506 ns" { VGAsingl:inst|add~342 VGAsingl:inst|add~343 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(0.651 ns) 3.551 ns VGAsingl:inst\|LL~387 7 COMB LCCOMB_X24_Y2_N2 1 " "Info: 7: + IC(0.689 ns) + CELL(0.651 ns) = 3.551 ns; Loc. = LCCOMB_X24_Y2_N2; Fanout = 1; COMB Node = 'VGAsingl:inst\|LL~387'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.340 ns" { VGAsingl:inst|add~343 VGAsingl:inst|LL~387 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.659 ns VGAsingl:inst\|LL\[7\] 8 REG LCFF_X24_Y2_N3 9 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 3.659 ns; Loc. = LCFF_X24_Y2_N3; Fanout = 9; REG Node = 'VGAsingl:inst\|LL\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.108 ns" { VGAsingl:inst|LL~387 VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.223 ns ( 60.75 % ) " "Info: Total cell delay = 2.223 ns ( 60.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.436 ns ( 39.25 % ) " "Info: Total interconnect delay = 1.436 ns ( 39.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "3.659 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|add~336 VGAsingl:inst|add~338 VGAsingl:inst|add~340 VGAsingl:inst|add~342 VGAsingl:inst|add~343 VGAsingl:inst|LL~387 VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.659 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|add~336 VGAsingl:inst|add~338 VGAsingl:inst|add~340 VGAsingl:inst|add~342 VGAsingl:inst|add~343 VGAsingl:inst|LL~387 VGAsingl:inst|LL[7] } { 0.000ns 0.747ns 0.000ns 0.000ns 0.000ns 0.000ns 0.689ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.190ns 0.086ns 0.506ns 0.651ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.440 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { clk } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.970 ns) 3.065 ns VGAsingl:inst\|FS\[5\] 3 REG LCFF_X1_Y6_N27 3 " "Info: 3: + IC(0.812 ns) + CELL(0.970 ns) = 3.065 ns; Loc. = LCFF_X1_Y6_N27; Fanout = 3; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.782 ns" { clk~clkctrl VGAsingl:inst|FS[5] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.000 ns) 3.891 ns VGAsingl:inst\|FS\[5\]~clkctrl 4 COMB CLKCTRL_G1 5 " "Info: 4: + IC(0.826 ns) + CELL(0.000 ns) = 3.891 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'VGAsingl:inst\|FS\[5\]~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.826 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.843 ns) + CELL(0.970 ns) 5.704 ns VGAsingl:inst\|CC\[4\] 5 REG LCFF_X27_Y4_N11 7 " "Info: 5: + IC(0.843 ns) + CELL(0.970 ns) = 5.704 ns; Loc. = LCFF_X27_Y4_N11; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.813 ns" { VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 6.922 ns VGAsingl:inst\|CC\[4\]~clkctrl 6 COMB CLKCTRL_G6 9 " "Info: 6: + IC(1.218 ns) + CELL(0.000 ns) = 6.922 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst\|CC\[4\]~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.218 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 8.440 ns VGAsingl:inst\|LL\[7\] 7 REG LCFF_X24_Y2_N3 9 " "Info: 7: + IC(0.852 ns) + CELL(0.666 ns) = 8.440 ns; Loc. = LCFF_X24_Y2_N3; Fanout = 9; REG Node = 'VGAsingl:inst\|LL\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.518 ns" { VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 44.38 % ) " "Info: Total cell delay = 3.746 ns ( 44.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.694 ns ( 55.62 % ) " "Info: Total interconnect delay = 4.694 ns ( 55.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.440 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { clk } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.812 ns) + CELL(0.970 ns) 3.065 ns VGAsingl:inst\|FS\[5\] 3 REG LCFF_X1_Y6_N27 3 " "Info: 3: + IC(0.812 ns) + CELL(0.970 ns) = 3.065 ns; Loc. = LCFF_X1_Y6_N27; Fanout = 3; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.782 ns" { clk~clkctrl VGAsingl:inst|FS[5] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.000 ns) 3.891 ns VGAsingl:inst\|FS\[5\]~clkctrl 4 COMB CLKCTRL_G1 5 " "Info: 4: + IC(0.826 ns) + CELL(0.000 ns) = 3.891 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'VGAsingl:inst\|FS\[5\]~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.826 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.843 ns) + CELL(0.970 ns) 5.704 ns VGAsingl:inst\|CC\[4\] 5 REG LCFF_X27_Y4_N11 7 " "Info: 5: + IC(0.843 ns) + CELL(0.970 ns) = 5.704 ns; Loc. = LCFF_X27_Y4_N11; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.813 ns" { VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.218 ns) + CELL(0.000 ns) 6.922 ns VGAsingl:inst\|CC\[4\]~clkctrl 6 COMB CLKCTRL_G6 9 " "Info: 6: + IC(1.218 ns) + CELL(0.000 ns) = 6.922 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst\|CC\[4\]~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.218 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.666 ns) 8.440 ns VGAsingl:inst\|LL\[3\] 7 REG LCFF_X24_Y2_N11 7 " "Info: 7: + IC(0.852 ns) + CELL(0.666 ns) = 8.440 ns; Loc. = LCFF_X24_Y2_N11; Fanout = 7; REG Node = 'VGAsingl:inst\|LL\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.518 ns" { VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 44.38 % ) " "Info: Total cell delay = 3.746 ns ( 44.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.694 ns ( 55.62 % ) " "Info: Total interconnect delay = 4.694 ns ( 55.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "3.659 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|add~336 VGAsingl:inst|add~338 VGAsingl:inst|add~340 VGAsingl:inst|add~342 VGAsingl:inst|add~343 VGAsingl:inst|LL~387 VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.659 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|add~336 VGAsingl:inst|add~338 VGAsingl:inst|add~340 VGAsingl:inst|add~342 VGAsingl:inst|add~343 VGAsingl:inst|LL~387 VGAsingl:inst|LL[7] } { 0.000ns 0.747ns 0.000ns 0.000ns 0.000ns 0.000ns 0.689ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.190ns 0.086ns 0.506ns 0.651ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[7] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "8.440 ns" { clk clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.440 ns" { clk clk~combout clk~clkctrl VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } { 0.000ns 0.000ns 0.143ns 0.812ns 0.826ns 0.843ns 1.218ns 0.852ns } { 0.000ns 1.140ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}