vga.fit.qmsg

FPGA EP2C5 VGA 使用verilogHdl

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.821 ns register register " "Info: Estimated most critical path is register to register delay of 3.821 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|LL\[0\] 1 REG LAB_X24_Y2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X24_Y2; Fanout = 7; REG Node = 'VGAsingl:inst\|LL\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|LL[0] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.621 ns) 1.269 ns VGAsingl:inst\|add~330 2 COMB LAB_X24_Y2 2 " "Info: 2: + IC(0.648 ns) + CELL(0.621 ns) = 1.269 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~330'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "1.269 ns" { VGAsingl:inst|LL[0] VGAsingl:inst|add~330 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.430 ns VGAsingl:inst\|add~332 3 COMB LAB_X24_Y2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.161 ns) = 1.430 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~332'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~330 VGAsingl:inst|add~332 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.591 ns VGAsingl:inst\|add~334 4 COMB LAB_X24_Y2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.161 ns) = 1.591 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~334'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~332 VGAsingl:inst|add~334 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.752 ns VGAsingl:inst\|add~336 5 COMB LAB_X24_Y2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.161 ns) = 1.752 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~336'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~334 VGAsingl:inst|add~336 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 1.913 ns VGAsingl:inst\|add~338 6 COMB LAB_X24_Y2 2 " "Info: 6: + IC(0.000 ns) + CELL(0.161 ns) = 1.913 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~338'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~336 VGAsingl:inst|add~338 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.074 ns VGAsingl:inst\|add~340 7 COMB LAB_X24_Y2 2 " "Info: 7: + IC(0.000 ns) + CELL(0.161 ns) = 2.074 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~340'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~338 VGAsingl:inst|add~340 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.235 ns VGAsingl:inst\|add~342 8 COMB LAB_X24_Y2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.161 ns) = 2.235 ns; Loc. = LAB_X24_Y2; Fanout = 2; COMB Node = 'VGAsingl:inst\|add~342'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~340 VGAsingl:inst|add~342 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 2.396 ns VGAsingl:inst\|add~344 9 COMB LAB_X24_Y2 1 " "Info: 9: + IC(0.000 ns) + CELL(0.161 ns) = 2.396 ns; Loc. = LAB_X24_Y2; Fanout = 1; COMB Node = 'VGAsingl:inst\|add~344'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.161 ns" { VGAsingl:inst|add~342 VGAsingl:inst|add~344 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.902 ns VGAsingl:inst\|add~345 10 COMB LAB_X24_Y2 1 " "Info: 10: + IC(0.000 ns) + CELL(0.506 ns) = 2.902 ns; Loc. = LAB_X24_Y2; Fanout = 1; COMB Node = 'VGAsingl:inst\|add~345'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.506 ns" { VGAsingl:inst|add~344 VGAsingl:inst|add~345 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 3.713 ns VGAsingl:inst\|LL~388 11 COMB LAB_X24_Y2 1 " "Info: 11: + IC(0.160 ns) + CELL(0.651 ns) = 3.713 ns; Loc. = LAB_X24_Y2; Fanout = 1; COMB Node = 'VGAsingl:inst\|LL~388'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.811 ns" { VGAsingl:inst|add~345 VGAsingl:inst|LL~388 } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.821 ns VGAsingl:inst\|LL\[8\] 12 REG LAB_X24_Y2 6 " "Info: 12: + IC(0.000 ns) + CELL(0.108 ns) = 3.821 ns; Loc. = LAB_X24_Y2; Fanout = 6; REG Node = 'VGAsingl:inst\|LL\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "0.108 ns" { VGAsingl:inst|LL~388 VGAsingl:inst|LL[8] } "NODE_NAME" } "" } } { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.013 ns ( 78.85 % ) " "Info: Total cell delay = 3.013 ns ( 78.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.808 ns ( 21.15 % ) " "Info: Total interconnect delay = 0.808 ns ( 21.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "3.821 ns" { VGAsingl:inst|LL[0] VGAsingl:inst|add~330 VGAsingl:inst|add~332 VGAsingl:inst|add~334 VGAsingl:inst|add~336 VGAsingl:inst|add~338 VGAsingl:inst|add~340 VGAsingl:inst|add~342 VGAsingl:inst|add~344 VGAsingl:inst|add~345 VGAsingl:inst|LL~388 VGAsingl:inst|LL[8] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_PRELIMINARY_TIMING" "EP2C5Q208C8 " "Warning: Timing characteristics of device EP2C5Q208C8 are preliminary" {  } {  } 0 0 "Timing characteristics of device %1!s! are preliminary" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "r 0 " "Warning: Pin \"r\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "g 0 " "Warning: Pin \"g\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "b 0 " "Warning: Pin \"b\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "HS 0 " "Warning: Pin \"HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Warning" "WDAT_NO_LOADING_SPECIFIED_ON_PIN" "VS 0 " "Warning: Pin \"VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 28 19:37:35 2006 " "Info: Processing ended: Sun May 28 19:37:35 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}