vga.fit.qmsg

FPGA EP2C5 VGA 使用verilogHdl

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 28 19:37:31 2006 " "Info: Processing started: Sun May 28 19:37:31 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off VGA -c VGA " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off VGA -c VGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "VGA EP2C5Q208C8 " "Info: Selected device EP2C5Q208C8 for design \"VGA\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208C8 " "Info: Device EP2C8Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 23 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "VGA.bdf" "" { Schematic "G:/Quartus II/ep2c5/VGA_2c5/VGA.bdf" { { 104 -48 120 120 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { clk } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "VGAsingl:inst\|CC\[4\]  " "Info: Automatically promoted node VGAsingl:inst\|CC\[4\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|GRBX\[2\]~516 " "Info: Destination node VGAsingl:inst\|GRBX\[2\]~516" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|GRBX\[2\]~516" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|GRBX[2]~516 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|GRBX[2]~516 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|LessThan~988 " "Info: Destination node VGAsingl:inst\|LessThan~988" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|LessThan~988" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|LessThan~988 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|LessThan~988 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|GRBX\[3\]~517 " "Info: Destination node VGAsingl:inst\|GRBX\[3\]~517" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|GRBX\[3\]~517" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|GRBX[3]~517 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|GRBX[3]~517 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|GRBX\[1\]~518 " "Info: Destination node VGAsingl:inst\|GRBX\[1\]~518" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|GRBX\[1\]~518" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|GRBX[1]~518 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|GRBX[1]~518 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|GRBX\[1\]~519 " "Info: Destination node VGAsingl:inst\|GRBX\[1\]~519" {  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|GRBX\[1\]~519" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|GRBX[1]~519 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|GRBX[1]~519 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|add~355 " "Info: Destination node VGAsingl:inst\|add~355" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|add~355" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|add~355 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|add~355 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 45 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|CC\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|CC[4] } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|CC[4] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "VGAsingl:inst\|FS\[5\]  " "Info: Automatically promoted node VGAsingl:inst\|FS\[5\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGAsingl:inst\|add~367 " "Info: Destination node VGAsingl:inst\|add~367" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|add~367" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|add~367 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|add~367 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rtl~144 " "Info: Destination node rtl~144" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~144" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { rtl~144 } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { rtl~144 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "VGAsingl.vhd" "" { Text "G:/Quartus II/ep2c5/VGA_2c5/VGAsingl.vhd" 10 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|FS\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "G:/Quartus II/ep2c5/VGA_2c5/db/VGA.quartus_db" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/" "" "" { VGAsingl:inst|FS[5] } "NODE_NAME" } "" } } { "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" { Floorplan "G:/Quartus II/ep2c5/VGA_2c5/VGA.fld" "" "" { VGAsingl:inst|FS[5] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}