vga.tan.rpt

FPGA EP2C5 VGA 使用verilogHdl

    Info: Assuming node "key" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "VGAsingl:inst|FS[5]" as buffer
    Info: Detected ripple clock "VGAsingl:inst|CC[4]" as buffer
Info: Clock "clk" has Internal fmax of 254.91 MHz between source register "VGAsingl:inst|LL[3]" and destination register "VGAsingl:inst|LL[7]" (period= 3.923 ns)
    Info: + Longest register to register delay is 3.659 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y2_N11; Fanout = 7; REG Node = 'VGAsingl:inst|LL[3]'
        Info: 2: + IC(0.747 ns) + CELL(0.596 ns) = 1.343 ns; Loc. = LCCOMB_X24_Y2_N10; Fanout = 2; COMB Node = 'VGAsingl:inst|add~336'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.429 ns; Loc. = LCCOMB_X24_Y2_N12; Fanout = 2; COMB Node = 'VGAsingl:inst|add~338'
        Info: 4: + IC(0.000 ns) + CELL(0.190 ns) = 1.619 ns; Loc. = LCCOMB_X24_Y2_N14; Fanout = 2; COMB Node = 'VGAsingl:inst|add~340'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.705 ns; Loc. = LCCOMB_X24_Y2_N16; Fanout = 2; COMB Node = 'VGAsingl:inst|add~342'
        Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 2.211 ns; Loc. = LCCOMB_X24_Y2_N18; Fanout = 1; COMB Node = 'VGAsingl:inst|add~343'
        Info: 7: + IC(0.689 ns) + CELL(0.651 ns) = 3.551 ns; Loc. = LCCOMB_X24_Y2_N2; Fanout = 1; COMB Node = 'VGAsingl:inst|LL~387'
        Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 3.659 ns; Loc. = LCFF_X24_Y2_N3; Fanout = 9; REG Node = 'VGAsingl:inst|LL[7]'
        Info: Total cell delay = 2.223 ns ( 60.75 % )
        Info: Total interconnect delay = 1.436 ns ( 39.25 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 8.440 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.812 ns) + CELL(0.970 ns) = 3.065 ns; Loc. = LCFF_X1_Y6_N27; Fanout = 3; REG Node = 'VGAsingl:inst|FS[5]'
            Info: 4: + IC(0.826 ns) + CELL(0.000 ns) = 3.891 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'VGAsingl:inst|FS[5]~clkctrl'
            Info: 5: + IC(0.843 ns) + CELL(0.970 ns) = 5.704 ns; Loc. = LCFF_X27_Y4_N11; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
            Info: 6: + IC(1.218 ns) + CELL(0.000 ns) = 6.922 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst|CC[4]~clkctrl'
            Info: 7: + IC(0.852 ns) + CELL(0.666 ns) = 8.440 ns; Loc. = LCFF_X24_Y2_N3; Fanout = 9; REG Node = 'VGAsingl:inst|LL[7]'
            Info: Total cell delay = 3.746 ns ( 44.38 % )
            Info: Total interconnect delay = 4.694 ns ( 55.62 % )
        Info: - Longest clock path from clock "clk" to source register is 8.440 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.812 ns) + CELL(0.970 ns) = 3.065 ns; Loc. = LCFF_X1_Y6_N27; Fanout = 3; REG Node = 'VGAsingl:inst|FS[5]'
            Info: 4: + IC(0.826 ns) + CELL(0.000 ns) = 3.891 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'VGAsingl:inst|FS[5]~clkctrl'
            Info: 5: + IC(0.843 ns) + CELL(0.970 ns) = 5.704 ns; Loc. = LCFF_X27_Y4_N11; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
            Info: 6: + IC(1.218 ns) + CELL(0.000 ns) = 6.922 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst|CC[4]~clkctrl'
            Info: 7: + IC(0.852 ns) + CELL(0.666 ns) = 8.440 ns; Loc. = LCFF_X24_Y2_N11; Fanout = 7; REG Node = 'VGAsingl:inst|LL[3]'
            Info: Total cell delay = 3.746 ns ( 44.38 % )
            Info: Total interconnect delay = 4.694 ns ( 55.62 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: Clock "key" Internal fmax is restricted to 360.1 MHz between source register "VGAsingl:inst|MMD[0]" and destination register "VGAsingl:inst|MMD[1]"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.236 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y4_N21; Fanout = 5; REG Node = 'VGAsingl:inst|MMD[0]'
            Info: 2: + IC(0.481 ns) + CELL(0.647 ns) = 1.128 ns; Loc. = LCCOMB_X26_Y4_N28; Fanout = 1; COMB Node = 'rtl~1'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.236 ns; Loc. = LCFF_X26_Y4_N29; Fanout = 5; REG Node = 'VGAsingl:inst|MMD[1]'
            Info: Total cell delay = 0.755 ns ( 61.08 % )
            Info: Total interconnect delay = 0.481 ns ( 38.92 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "key" to destination register is 7.384 ns
                Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_103; Fanout = 5; CLK Node = 'key'
                Info: 2: + IC(5.714 ns) + CELL(0.666 ns) = 7.384 ns; Loc. = LCFF_X26_Y4_N29; Fanout = 5; REG Node = 'VGAsingl:inst|MMD[1]'
                Info: Total cell delay = 1.670 ns ( 22.62 % )
                Info: Total interconnect delay = 5.714 ns ( 77.38 % )
            Info: - Longest clock path from clock "key" to source register is 7.384 ns
                Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_103; Fanout = 5; CLK Node = 'key'
                Info: 2: + IC(5.714 ns) + CELL(0.666 ns) = 7.384 ns; Loc. = LCFF_X26_Y4_N21; Fanout = 5; REG Node = 'VGAsingl:inst|MMD[0]'
                Info: Total cell delay = 1.670 ns ( 22.62 % )
                Info: Total interconnect delay = 5.714 ns ( 77.38 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "r" through register "VGAsingl:inst|LL[6]" is 20.035 ns
    Info: + Longest clock path from clock "clk" to source register is 8.440 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.812 ns) + CELL(0.970 ns) = 3.065 ns; Loc. = LCFF_X1_Y6_N27; Fanout = 3; REG Node = 'VGAsingl:inst|FS[5]'
        Info: 4: + IC(0.826 ns) + CELL(0.000 ns) = 3.891 ns; Loc. = CLKCTRL_G1; Fanout = 5; COMB Node = 'VGAsingl:inst|FS[5]~clkctrl'
        Info: 5: + IC(0.843 ns) + CELL(0.970 ns) = 5.704 ns; Loc. = LCFF_X27_Y4_N11; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
        Info: 6: + IC(1.218 ns) + CELL(0.000 ns) = 6.922 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst|CC[4]~clkctrl'
        Info: 7: + IC(0.852 ns) + CELL(0.666 ns) = 8.440 ns; Loc. = LCFF_X24_Y2_N25; Fanout = 9; REG Node = 'VGAsingl:inst|LL[6]'
        Info: Total cell delay = 3.746 ns ( 44.38 % )
        Info: Total interconnect delay = 4.694 ns ( 55.62 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 11.291 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y2_N25; Fanout = 9; REG Node = 'VGAsingl:inst|LL[6]'
        Info: 2: + IC(1.220 ns) + CELL(0.614 ns) = 1.834 ns; Loc. = LCCOMB_X24_Y3_N18; Fanout = 2; COMB Node = 'VGAsingl:inst|GRBY[2]~813'
        Info: 3: + IC(0.384 ns) + CELL(0.616 ns) = 2.834 ns; Loc. = LCCOMB_X24_Y3_N2; Fanout = 1; COMB Node = 'VGAsingl:inst|GRBY[2]~815'
        Info: 4: + IC(0.376 ns) + CELL(0.624 ns) = 3.834 ns; Loc. = LCCOMB_X24_Y3_N10; Fanout = 1; COMB Node = 'VGAsingl:inst|GRBY[2]~817'
        Info: 5: + IC(1.427 ns) + CELL(0.651 ns) = 5.912 ns; Loc. = LCCOMB_X26_Y4_N0; Fanout = 1; COMB Node = 'VGAsingl:inst|GRBP[2]~752'
        Info: 6: + IC(0.364 ns) + CELL(0.615 ns) = 6.891 ns; Loc. = LCCOMB_X26_Y4_N16; Fanout = 1; COMB Node = 'VGAsingl:inst|R'
        Info: 7: + IC(1.284 ns) + CELL(3.116 ns) = 11.291 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'r'
        Info: Total cell delay = 6.236 ns ( 55.23 % )
        Info: Total interconnect delay = 5.055 ns ( 44.77 % )
Info: Longest tpd from source pin "key" to destination pin "b" is 11.941 ns
    Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_103; Fanout = 5; CLK Node = 'key'
    Info: 2: + IC(5.793 ns) + CELL(0.647 ns) = 7.444 ns; Loc. = LCCOMB_X26_Y4_N24; Fanout = 1; COMB Node = 'VGAsingl:inst|B'
    Info: 3: + IC(1.381 ns) + CELL(3.116 ns) = 11.941 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'b'
    Info: Total cell delay = 4.767 ns ( 39.92 % )
    Info: Total interconnect delay = 7.174 ns ( 60.08 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun May 28 19:37:41 2006
    Info: Elapsed time: 00:00:02