vga.tan.summary

FPGA EP2C5 VGA 使用verilogHdl

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.035 ns
From           : VGAsingl:inst|LL[6]
To             : r
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.941 ns
From           : key
To             : b
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 254.91 MHz ( period = 3.923 ns )
From           : VGAsingl:inst|LL[3]
To             : VGAsingl:inst|LL[7]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'key'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 360.10 MHz ( period = 2.777 ns )
From           : VGAsingl:inst|MMD[0]
To             : VGAsingl:inst|MMD[1]
From Clock     : key
To Clock       : key
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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