__projnav.log

接VGA 显示器和鼠标

Project Navigator Auto-Make Log File
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Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file E:\work\digital_sward\sub_DEMO\subgame/cannon.vhd, automatic determination of correct order of compilation of files in project file cannon_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file E:\work\digital_sward\sub_DEMO\subgame/cannon.vhd in Library work.
ERROR:HDLParsers:837 - E:\work\digital_sward\sub_DEMO\subgame/cannon.vhd Line 24. Index size for dimension 1 of move is not 11.
ERROR:HDLParsers:164 - E:\work\digital_sward\sub_DEMO\subgame/cannon.vhd Line 43. parse error, unexpected END, expecting IDENTIFIER or STRING_LITERAL
--> 

Total memory usage is 47796 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was e:/work/coreban/subgame/Top.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Top.vhd
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/Top.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Top.vhd
WARNING:HDLParsers:3215 - Unit work/VGASIG is now defined in a different file: was e:/work/coreban/subgame/vgasig.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd
WARNING:HDLParsers:3215 - Unit work/VGASIG/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/vgasig.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd
WARNING:HDLParsers:3215 - Unit work/MOUSE is now defined in a different file: was e:/work/coreban/subgame/Mouse.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd
WARNING:HDLParsers:3215 - Unit work/MOUSE/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/Mouse.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT64 is now defined in a different file: was e:/work/coreban/subgame/Count64.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT64/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/Count64.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd
WARNING:HDLParsers:3215 - Unit work/TARGET is now defined in a different file: was e:/work/coreban/subgame/target.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/target.vhd
WARNING:HDLParsers:3215 - Unit work/TARGET/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/target.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/target.vhd
WARNING:HDLParsers:3215 - Unit work/BALL is now defined in a different file: was e:/work/coreban/subgame/ball.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/ball.vhd
WARNING:HDLParsers:3215 - Unit work/BALL/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/ball.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/ball.vhd
WARNING:HDLParsers:3215 - Unit work/BOARD is now defined in a different file: was e:/work/coreban/subgame/board.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/board.vhd
WARNING:HDLParsers:3215 - Unit work/BOARD/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/board.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/board.vhd
WARNING:HDLParsers:3215 - Unit work/FRAME is now defined in a different file: was e:/work/coreban/subgame/frame.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/frame.vhd
WARNING:HDLParsers:3215 - Unit work/FRAME/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/frame.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/frame.vhd
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/frame.vhd in Library work.
Architecture behavioral of Entity frame is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/board.vhd in Library work.
Architecture behavioral of Entity board is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/ball.vhd in Library work.
Architecture behavioral of Entity ball is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/target.vhd in Library work.
Architecture behavioral of Entity target is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd in Library work.
Architecture behavioral of Entity count64 is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd in Library work.
Architecture behavioral of Entity mouse is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd in Library work.
Architecture behavioral of Entity vgasig is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/Top.vhd in Library work.
Architecture behavioral of Entity top is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 12: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 9: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <frame> (Architecture <behavioral>).
Entity <frame> analyzed. Unit <frame> generated.

Analyzing Entity <board> (Architecture <behavioral>).
Entity <board> analyzed. Unit <board> generated.

Analyzing Entity <ball> (Architecture <behavioral>).
Entity <ball> analyzed. Unit <ball> generated.

Analyzing Entity <target> (Architecture <behavioral>).
Entity <target> analyzed. Unit <target> generated.

Analyzing Entity <count64> (Architecture <behavioral>).
Entity <count64> analyzed. Unit <count64> generated.

Analyzing Entity <mouse> (Architecture <behavioral>).
Entity <mouse> analyzed. Unit <mouse> generated.

Analyzing Entity <vgasig> (Architecture <behavioral>).
Entity <vgasig> analyzed. Unit <vgasig> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vgasig>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd.
    Found 1-bit register for signal <vsyncb>.
    Found 1-bit register for signal <hsyncb>.
    Found 11-bit comparator less for signal <$n0008> created at line 43.
    Found 11-bit comparator less for signal <$n0009> created at line 60.
    Found 10-bit adder for signal <$n0012> created at line 44.
    Found 10-bit adder for signal <$n0013> created at line 61.
    Found 11-bit comparator greatequal for signal <$n0014> created at line 77.
    Found 11-bit comparator less for signal <$n0015> created at line 77.
    Found 11-bit comparator greatequal for signal <$n0016> created at line 94.
    Found 11-bit comparator less for signal <$n0017> created at line 94.
    Found 10-bit register for signal <hcnt>.
    Found 10-bit register for signal <vcnt>.
    Summary:
	inferred  22 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   6 Comparator(s).
Unit <vgasig> synthesized.


Synthesizing Unit <mouse>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd.
WARNING:Xst:646 - Signal <packet_good> is assigned but never used.
WARNING:Xst:646 - Signal <q<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <clean_clk> is never used or assigned.
WARNING:Xst:1780 - Signal <n_rise> is never used or assigned.
WARNING:Xst:1780 - Signal <n_fall> is never used or assigned.
    Register <risesig<0>> equivalent to <fallsig<0>> has been removed
    Found finite state machine <FSM_0> for signal <m2_state>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 28                                             |
    | Inputs             | 7                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | m2_reset                                       |
    | Power Up State     | m2_reset                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <q<6>> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <q<19>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 1-bit tristate buffer for signal <ps2_clk>.
    Found 1-bit tristate buffer for signal <ps2_data>.
    Found 1-bit register for signal <right_button>.
    Found 1-bit register for signal <left_button>.
    Found 10-bit register for signal <mousex>.
    Found 10-bit register for signal <mousey>.
    Found 10-bit adder for signal <$n0032> created at line 270.
    Found 10-bit adder for signal <$n0048> created at line 287.
    Found 10-bit adder for signal <$n0053> created at line 304.
    Found 11-bit comparator greatequal for signal <$n0054> created at line 282.
    Found 11-bit comparator lessequal for signal <$n0055> created at line 283.
    Found 11-bit comparator greatequal for signal <$n0056> created at line 299.
    Found 11-bit comparator lessequal for signal <$n0057> created at line 300.
    Found 6-bit up counter for signal <bitcount>.
    Found 3-bit register for signal <fallsig>.
    Found 10-bit register for signal <mousexx>.
    Found 10-bit register for signal <mouseyy>.
    Found 33-bit register for signal <q>.
    Found 2-bit register for signal <risesig<2:1>>.
    Found 9-bit up counter for signal <watchdog_timer_count>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  60 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred   2 Tristate(s).
Unit <mouse> synthesized.


Synthesizing Unit <count64>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd.
    Found 7-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <count64> synthesized.


Synthesizing Unit <target>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/target.vhd.
    Found 8-bit adder for signal <$n0008> created at line 48.
    Found 10-bit adder for signal <$n0009>.
    Found 10-bit subtractor for signal <$n0010> created at line 48.
    Found 11-bit comparator lessequal for signal <$n0013> created at line 99.
    Found 10-bit comparator greater for signal <$n0017> created at line 48.
    Found 10-bit comparator less for signal <$n0018> created at line 48.
    Found 11-bit comparator greatequal for signal <$n0019> created at line 48.
    Found 11-bit comparator lessequal for signal <$n0020> created at line 48.
    Found 11-bit comparator greatequal for signal <$n0021> created at line 84.
    Found 11-bit comparator lessequal for signal <$n0022> created at line 85.
    Found 10-bit adder for signal <$n0023> created at line 100.
    Found 10-bit comparator greatequal for signal <$n0024> created at line 100.
    Found 10-bit subtractor for signal <$n0025> created at line 100.
    Found 10-bit comparator lessequal for signal <$n0026> created at line 100.
    Found 1-bit register for signal <hit>.
    Found 10-bit up accumulator for signal <loc>.
    Found 10-bit register for signal <mov_x>.
    Found 8-bit register for signal <rgbout>.
    Found 6-bit up counter for signal <sampcnt>.
    Found 10-bit register for signal <tempmov>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Accumulator(s).
	inferred   9 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   9 Comparator(s).
	inferred  10 Multiplexer(s).
Unit <target> synthesized.


Synthesizing Unit <ball>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/ball.vhd.
    Found 8-bit register for signal <ballrgb>.
    Found 9-bit adder for signal <$n0019> created at line 52.
    Found 9-bit adder for signal <$n0020> created at line 52.
    Found 8-bit adder for signal <$n0021> created at line 52.