__projnav.log

接VGA 显示器和鼠标

Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/work/coreban/subgame/frame.vhd in Library work.
Entity <frame> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/board.vhd in Library work.
Entity <board> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/ball.vhd in Library work.
Entity <ball> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/target.vhd in Library work.
Entity <target> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/Count64.vhd in Library work.
Entity <count64> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/Mouse.vhd in Library work.
Entity <mouse> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/vgasig.vhd in Library work.
Entity <vgasig> (Architecture <Behavioral>) compiled.
Compiling vhdl file e:/work/coreban/subgame/Top.vhd in Library work.
Entity <top> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <Behavioral>).
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/subgame/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/subgame/Top.vhd line 12: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/subgame/Top.vhd line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/subgame/Top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/subgame/Top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - e:/work/coreban/subgame/Top.vhd line 9: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <frame> (Architecture <behavioral>).
Entity <frame> analyzed. Unit <frame> generated.

Analyzing Entity <board> (Architecture <behavioral>).
Entity <board> analyzed. Unit <board> generated.

Analyzing Entity <ball> (Architecture <behavioral>).
Entity <ball> analyzed. Unit <ball> generated.

Analyzing Entity <target> (Architecture <behavioral>).
Entity <target> analyzed. Unit <target> generated.

Analyzing Entity <count64> (Architecture <behavioral>).
Entity <count64> analyzed. Unit <count64> generated.

Analyzing Entity <mouse> (Architecture <behavioral>).
Entity <mouse> analyzed. Unit <mouse> generated.

Analyzing Entity <vgasig> (Architecture <behavioral>).
Entity <vgasig> analyzed. Unit <vgasig> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vgasig>.
    Related source file is e:/work/coreban/subgame/vgasig.vhd.
    Found 1-bit register for signal <vsyncb>.
    Found 1-bit register for signal <hsyncb>.
    Found 11-bit comparator less for signal <$n0008> created at line 43.
    Found 11-bit comparator less for signal <$n0009> created at line 60.
    Found 10-bit adder for signal <$n0012> created at line 44.
    Found 10-bit adder for signal <$n0013> created at line 61.
    Found 11-bit comparator greatequal for signal <$n0014> created at line 77.
    Found 11-bit comparator less for signal <$n0015> created at line 77.
    Found 11-bit comparator greatequal for signal <$n0016> created at line 94.
    Found 11-bit comparator less for signal <$n0017> created at line 94.
    Found 10-bit register for signal <hcnt>.
    Found 10-bit register for signal <vcnt>.
    Summary:
	inferred  22 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   6 Comparator(s).
Unit <vgasig> synthesized.


Synthesizing Unit <mouse>.
    Related source file is e:/work/coreban/subgame/Mouse.vhd.
WARNING:Xst:646 - Signal <packet_good> is assigned but never used.
WARNING:Xst:646 - Signal <q<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <clean_clk> is never used or assigned.
WARNING:Xst:1780 - Signal <n_rise> is never used or assigned.
WARNING:Xst:1780 - Signal <n_fall> is never used or assigned.
    Register <risesig<0>> equivalent to <fallsig<0>> has been removed
    Found finite state machine <FSM_0> for signal <m2_state>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 28                                             |
    | Inputs             | 7                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | m2_reset                                       |
    | Power Up State     | m2_reset                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <q<6>> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <q<19>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 1-bit tristate buffer for signal <ps2_clk>.
    Found 1-bit tristate buffer for signal <ps2_data>.
    Found 1-bit register for signal <right_button>.
    Found 1-bit register for signal <left_button>.
    Found 10-bit register for signal <mousex>.
    Found 10-bit register for signal <mousey>.
    Found 10-bit adder for signal <$n0032> created at line 270.
    Found 10-bit adder for signal <$n0048> created at line 287.
    Found 10-bit adder for signal <$n0053> created at line 304.
    Found 11-bit comparator greatequal for signal <$n0054> created at line 282.
    Found 11-bit comparator lessequal for signal <$n0055> created at line 283.
    Found 11-bit comparator greatequal for signal <$n0056> created at line 299.
    Found 11-bit comparator lessequal for signal <$n0057> created at line 300.
    Found 6-bit up counter for signal <bitcount>.
    Found 3-bit register for signal <fallsig>.
    Found 10-bit register for signal <mousexx>.
    Found 10-bit register for signal <mouseyy>.
    Found 33-bit register for signal <q>.
    Found 2-bit register for signal <risesig<2:1>>.
    Found 9-bit up counter for signal <watchdog_timer_count>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  60 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred   2 Tristate(s).
Unit <mouse> synthesized.


Synthesizing Unit <count64>.
    Related source file is e:/work/coreban/subgame/Count64.vhd.
    Found 7-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <count64> synthesized.


Synthesizing Unit <target>.
    Related source file is e:/work/coreban/subgame/target.vhd.
    Found 8-bit adder for signal <$n0008> created at line 48.
    Found 10-bit adder for signal <$n0009>.
    Found 10-bit subtractor for signal <$n0010> created at line 48.
    Found 11-bit comparator lessequal for signal <$n0013> created at line 99.
    Found 10-bit comparator greater for signal <$n0017> created at line 48.
    Found 10-bit comparator less for signal <$n0018> created at line 48.
    Found 11-bit comparator greatequal for signal <$n0019> created at line 48.
    Found 11-bit comparator lessequal for signal <$n0020> created at line 48.
    Found 11-bit comparator greatequal for signal <$n0021> created at line 84.
    Found 11-bit comparator lessequal for signal <$n0022> created at line 85.
    Found 10-bit adder for signal <$n0023> created at line 100.
    Found 10-bit comparator greatequal for signal <$n0024> created at line 100.
    Found 10-bit subtractor for signal <$n0025> created at line 100.
    Found 10-bit comparator lessequal for signal <$n0026> created at line 100.
    Found 1-bit register for signal <hit>.
    Found 10-bit up accumulator for signal <loc>.
    Found 10-bit register for signal <mov_x>.
    Found 8-bit register for signal <rgbout>.
    Found 6-bit up counter for signal <sampcnt>.
    Found 10-bit register for signal <tempmov>.
    Found 10 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   1 Accumulator(s).
	inferred   9 D-type flip-flop(s).
	inferred   5 Adder/Subtracter(s).
	inferred   9 Comparator(s).
	inferred  10 Multiplexer(s).
Unit <target> synthesized.


Synthesizing Unit <ball>.
    Related source file is e:/work/coreban/subgame/ball.vhd.
    Found 8-bit register for signal <ballrgb>.
    Found 9-bit adder for signal <$n0019> created at line 52.
    Found 9-bit adder for signal <$n0020> created at line 52.
    Found 8-bit adder for signal <$n0021> created at line 52.
    Found 8-bit adder for signal <$n0022> created at line 52.
    Found 7-bit adder for signal <$n0023> created at line 121.
    Found 10-bit adder for signal <$n0024> created at line 121.
    Found 10-bit subtractor for signal <$n0025> created at line 121.
    Found 11-bit adder for signal <$n0028> created at line 106.
    Found 10-bit subtractor for signal <$n0031> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0032> created at line 52.
    Found 10-bit adder for signal <$n0033> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0034> created at line 52.
    Found 10-bit subtractor for signal <$n0035> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0036> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0037> created at line 52.
    Found 10-bit subtractor for signal <$n0038> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0039> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0040> created at line 52.
    Found 10-bit subtractor for signal <$n0041> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0042> created at line 52.
    Found 10-bit adder for signal <$n0043> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0044> created at line 52.
    Found 10-bit subtractor for signal <$n0045> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0046> created at line 52.
    Found 10-bit adder for signal <$n0047> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0048> created at line 52.
    Found 10-bit subtractor for signal <$n0049> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0050> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0051> created at line 52.
    Found 10-bit subtractor for signal <$n0052> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0053> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0054> created at line 52.
    Found 10-bit subtractor for signal <$n0055> created at line 52.
    Found 10-bit comparator greatequal for signal <$n0056> created at line 52.
    Found 10-bit adder for signal <$n0057> created at line 52.
    Found 10-bit comparator lessequal for signal <$n0058> created at line 52.
    Found 11-bit adder for signal <$n0059> created at line 73.
    Found 10-bit adder for signal <$n0060> created at line 74.
    Found 10-bit comparator greatequal for signal <$n0063> created at line 121.
    Found 10-bit comparator lessequal for signal <$n0064> created at line 121.
    Found 10-bit subtractor for signal <$n0065> created at line 121.
    Found 11-bit register for signal <ball_xx>.
    Found 10-bit register for signal <ball_y>.
    Found 1-bit register for signal <bang>.
    Found 11-bit register for signal <increase>.
    Found 1-bit register for signal <lose>.
    Found 11-bit register for signal <move_x>.
    Found 10-bit register for signal <move_y>.
    Found 11 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred  23 Adder/Subtracter(s).
	inferred  18 Comparator(s).
	inferred  11 Multiplexer(s).
Unit <ball> synthesized.