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接VGA 显示器和鼠标

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'sysclk'
Delay:               1.243ns (Levels of Logic = 1)
  Source:            vgaclk (FF)
  Destination:       vgaclk (FF)
  Source Clock:      sysclk rising
  Destination Clock: sysclk rising

  Data Path: vgaclk to vgaclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             23   0.000   1.243  vgaclk (vgaclk)
     LUT1:I0->O            1   0.000   0.000  _n00031 (_n0003)
     FDC:D                     0.000          vgaclk
    ----------------------------------------
    Total                      1.243ns (0.000ns logic, 1.243ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clocknum_count_6:Q'
Delay:               2.358ns (Levels of Logic = 4)
  Source:            mousedata_watchdog_timer_count_7 (FF)
  Destination:       mousedata_bitcount_2 (FF)
  Source Clock:      clocknum_count_6:Q rising
  Destination Clock: clocknum_count_6:Q rising

  Data Path: mousedata_watchdog_timer_count_7 to mousedata_bitcount_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.000   0.465  mousedata_watchdog_timer_count_7 (mousedata_watchdog_timer_count_7)
     LUT3:I0->O            1   0.000   0.240  mousedata__n003512 (CHOICE146)
     LUT4_D:I3->LO         1   0.000   0.100  mousedata__n003519_SW0 (N29198)
     LUT4:I1->O           12   0.000   0.865  mousedata__n003519 (mousedata_watchdog_timer_done)
     LUT4:I0->O            6   0.000   0.688  mousedata__n01351 (mousedata__n0135)
     FDCPE:CE                  0.000          mousedata_bitcount_0
    ----------------------------------------
    Total                      2.358ns (0.000ns logic, 2.358ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'vgaclk:Q'
Delay:               2.112ns (Levels of Logic = 3)
  Source:            shwodata_hcnt_9 (FF)
  Destination:       shwodata_hcnt_5 (FF)
  Source Clock:      vgaclk:Q rising
  Destination Clock: vgaclk:Q rising

  Data Path: shwodata_hcnt_9 to shwodata_hcnt_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             18   0.000   1.066  shwodata_hcnt_9 (shwodata_hcnt_9)
     LUT2:I1->O            1   0.000   0.240  shwodata_Mcompar__n0008_Ker6857_SW0 (N26804)
     LUT4:I1->O           10   0.000   0.806  shwodata_Mcompar__n0008_Ker6857 (shwodata_Mcompar__n0008_N6859)
     LUT2:I0->O            1   0.000   0.000  shwodata__n0004<1>1 (shwodata__n0004<1>)
     FDC:D                     0.000          shwodata_hcnt_1
    ----------------------------------------
    Total                      2.112ns (0.000ns logic, 2.112ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'shwodata_hsyncb:Q'
Delay:               2.177ns (Levels of Logic = 4)
  Source:            shwodata_vcnt_3 (FF)
  Destination:       shwodata_vcnt_9 (FF)
  Source Clock:      shwodata_hsyncb:Q rising
  Destination Clock: shwodata_hsyncb:Q rising

  Data Path: shwodata_vcnt_3 to shwodata_vcnt_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             17   0.000   1.031  shwodata_vcnt_3 (shwodata_vcnt_3)
     LUT4:I3->O            1   0.000   0.240  shwodata_Mcompar__n0009_Ker705535_SW0 (N29031)
     LUT4_L:I3->LO         1   0.000   0.100  shwodata_Mcompar__n0009_Ker705535 (CHOICE164)
     LUT4:I2->O           10   0.000   0.806  shwodata_Mcompar__n0009_Ker705563 (shwodata_Mcompar__n0009_N7057)
     LUT2_L:I0->LO         1   0.000   0.000  shwodata__n0005<3>1 (shwodata__n0005<3>)
     FDC:D                     0.000          shwodata_vcnt_3
    ----------------------------------------
    Total                      2.177ns (0.000ns logic, 2.177ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'shwodata_vcnt_6:Q'
Delay:               2.972ns (Levels of Logic = 4)
  Source:            drawball_ball_xx_6 (FF)
  Destination:       drawball_move_x_10 (FF)
  Source Clock:      shwodata_vcnt_6:Q rising
  Destination Clock: shwodata_vcnt_6:Q rising

  Data Path: drawball_ball_xx_6 to drawball_move_x_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             15   0.000   0.960  drawball_ball_xx_6 (drawball_ball_xx_6)
     LUT4:I0->O            1   0.000   0.240  drawball__n002726 (CHOICE181)
     LUT4_L:I2->LO         1   0.000   0.100  drawball__n002735_SW0 (N29027)
     LUT4:I2->O           11   0.000   0.836  drawball__n002735 (drawball__n0027)
     LUT3:I0->O           11   0.000   0.836  drawball__n010748 (drawball__n0107)
     FDCE:CE                   0.000          drawball_move_x_2
    ----------------------------------------
    Total                      2.972ns (-0.000ns logic, 2.972ns route)
                                       (-0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'shwodata_vcnt_9:Q'
Delay:               1.704ns (Levels of Logic = 4)
  Source:            drawtarget_loc_3 (FF)
  Destination:       drawtarget_mov_x_9 (FF)
  Source Clock:      shwodata_vcnt_9:Q rising
  Destination Clock: shwodata_vcnt_9:Q rising

  Data Path: drawtarget_loc_3 to drawtarget_mov_x_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.000   0.658  drawtarget_loc_3 (drawtarget_loc_3)
     LUT4:I1->O            1   0.000   0.240  drawtarget__n00336 (CHOICE119)
     LUT4:I2->O            1   0.000   0.000  drawtarget__n003373_G (N29112)
     MUXF5:I1->O          10   0.000   0.806  drawtarget__n003373 (drawtarget__n0033)
     LUT3:I0->O            1   0.000   0.000  drawtarget_Mmux__n0006_Result<0>1 (drawtarget__n0006<0>)
     FDP:D                     0.000          drawtarget_mov_x_0
    ----------------------------------------
    Total                      1.704ns (0.000ns logic, 1.704ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clocknum_count_6:Q'
Offset:              2.827ns (Levels of Logic = 2)
  Source:            reset1 (PAD)
  Destination:       mousedata_mousexx_7 (FF)
  Destination Clock: clocknum_count_6:Q rising

  Data Path: reset1 to mousedata_mousexx_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           176   0.641   1.409  reset1_IBUF (reset1_IBUF)
     LUT2:I1->O            9   0.000   0.777  mousedata__n00241 (mousedata__n0024)
     FDE:CE                    0.000          mousedata_mousexx_1
    ----------------------------------------
    Total                      2.827ns (0.641ns logic, 2.186ns route)
                                       (22.7% logic, 77.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clocknum_count_6:Q'
Offset:              6.753ns (Levels of Logic = 2)
  Source:            mousedata_m2_state_FFd4 (FF)
  Destination:       ps2data (PAD)
  Source Clock:      clocknum_count_6:Q rising

  Data Path: mousedata_m2_state_FFd4 to ps2data
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.000   0.577  mousedata_m2_state_FFd4 (mousedata_m2_state_FFd4)
     LUT3:I0->O            1   0.000   0.240  mousedata_m2_state_Out21 (mousedata_ps2_data_hi_z)
     IOBUF:T->IO               5.936          ps2data_IOBUF (ps2data)
    ----------------------------------------
    Total                      6.753ns (5.936ns logic, 0.817ns route)
                                       (87.9% logic, 12.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'shwodata_hsyncb:Q'
Offset:              5.820ns (Levels of Logic = 1)
  Source:            shwodata_vsyncb (FF)
  Destination:       vsyncb (PAD)
  Source Clock:      shwodata_hsyncb:Q rising

  Data Path: shwodata_vsyncb to vsyncb
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              1   0.000   0.240  shwodata_vsyncb (shwodata_vsyncb)
     OBUF:I->O                 5.580          vsyncb_OBUF (vsyncb)
    ----------------------------------------
    Total                      5.820ns (5.580ns logic, 0.240ns route)
                                       (95.9% logic, 4.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'vgaclk:Q'
Offset:              6.622ns (Levels of Logic = 2)
  Source:            drawball_ballrgb_4 (FF)
  Destination:       rgb<5> (PAD)
  Source Clock:      vgaclk:Q rising

  Data Path: drawball_ballrgb_4 to rgb<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.000   0.465  drawball_ballrgb_4 (drawball_ballrgb_4)
     LUT3:I0->O            3   0.000   0.577  Mxor_rgb_Xo<11>1 (rgb_3_OBUF)
     OBUF:I->O                 5.580          rgb_3_OBUF (rgb<3>)
    ----------------------------------------
    Total                      6.622ns (5.580ns logic, 1.042ns route)
                                       (84.3% logic, 15.7% route)

=========================================================================
CPU : 27.15 / 28.70 s | Elapsed : 27.00 / 28.00 s
 
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Total memory usage is 81652 kilobytes