top.syr

接VGA 显示器和鼠标

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was e:/work/coreban/subgame/Top.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Top.vhd
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/Top.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Top.vhd
WARNING:HDLParsers:3215 - Unit work/VGASIG is now defined in a different file: was e:/work/coreban/subgame/vgasig.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd
WARNING:HDLParsers:3215 - Unit work/VGASIG/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/vgasig.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd
WARNING:HDLParsers:3215 - Unit work/MOUSE is now defined in a different file: was e:/work/coreban/subgame/Mouse.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd
WARNING:HDLParsers:3215 - Unit work/MOUSE/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/Mouse.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT64 is now defined in a different file: was e:/work/coreban/subgame/Count64.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd
WARNING:HDLParsers:3215 - Unit work/COUNT64/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/Count64.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd
WARNING:HDLParsers:3215 - Unit work/TARGET is now defined in a different file: was e:/work/coreban/subgame/target.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/target.vhd
WARNING:HDLParsers:3215 - Unit work/TARGET/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/target.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/target.vhd
WARNING:HDLParsers:3215 - Unit work/BALL is now defined in a different file: was e:/work/coreban/subgame/ball.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/ball.vhd
WARNING:HDLParsers:3215 - Unit work/BALL/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/ball.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/ball.vhd
WARNING:HDLParsers:3215 - Unit work/BOARD is now defined in a different file: was e:/work/coreban/subgame/board.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/board.vhd
WARNING:HDLParsers:3215 - Unit work/BOARD/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/board.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/board.vhd
WARNING:HDLParsers:3215 - Unit work/FRAME is now defined in a different file: was e:/work/coreban/subgame/frame.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/frame.vhd
WARNING:HDLParsers:3215 - Unit work/FRAME/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subgame/frame.vhd, now is E:/work/digital_sward/sub_DEMO/subgame/frame.vhd
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/frame.vhd in Library work.
Architecture behavioral of Entity frame is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/board.vhd in Library work.
Architecture behavioral of Entity board is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/ball.vhd in Library work.
Architecture behavioral of Entity ball is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/target.vhd in Library work.
Architecture behavioral of Entity target is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/Count64.vhd in Library work.
Architecture behavioral of Entity count64 is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd in Library work.
Architecture behavioral of Entity mouse is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd in Library work.
Architecture behavioral of Entity vgasig is up to date.
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subgame/Top.vhd in Library work.
Architecture behavioral of Entity top is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 11: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 12: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 15: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 16: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - E:/work/digital_sward/sub_DEMO/subgame/Top.vhd line 9: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <frame> (Architecture <behavioral>).
Entity <frame> analyzed. Unit <frame> generated.

Analyzing Entity <board> (Architecture <behavioral>).
Entity <board> analyzed. Unit <board> generated.

Analyzing Entity <ball> (Architecture <behavioral>).
Entity <ball> analyzed. Unit <ball> generated.

Analyzing Entity <target> (Architecture <behavioral>).
Entity <target> analyzed. Unit <target> generated.

Analyzing Entity <count64> (Architecture <behavioral>).
Entity <count64> analyzed. Unit <count64> generated.

Analyzing Entity <mouse> (Architecture <behavioral>).
Entity <mouse> analyzed. Unit <mouse> generated.

Analyzing Entity <vgasig> (Architecture <behavioral>).
Entity <vgasig> analyzed. Unit <vgasig> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vgasig>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/vgasig.vhd.
    Found 1-bit register for signal <vsyncb>.
    Found 1-bit register for signal <hsyncb>.
    Found 11-bit comparator less for signal <$n0008> created at line 43.
    Found 11-bit comparator less for signal <$n0009> created at line 60.
    Found 10-bit adder for signal <$n0012> created at line 44.
    Found 10-bit adder for signal <$n0013> created at line 61.
    Found 11-bit comparator greatequal for signal <$n0014> created at line 77.
    Found 11-bit comparator less for signal <$n0015> created at line 77.
    Found 11-bit comparator greatequal for signal <$n0016> created at line 94.
    Found 11-bit comparator less for signal <$n0017> created at line 94.
    Found 10-bit register for signal <hcnt>.
    Found 10-bit register for signal <vcnt>.
    Summary:
	inferred  22 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   6 Comparator(s).
Unit <vgasig> synthesized.


Synthesizing Unit <mouse>.
    Related source file is E:/work/digital_sward/sub_DEMO/subgame/Mouse.vhd.
WARNING:Xst:646 - Signal <packet_good> is assigned but never used.
WARNING:Xst:646 - Signal <q<0>> is assigned but never used.
WARNING:Xst:1780 - Signal <clean_clk> is never used or assigned.
WARNING:Xst:1780 - Signal <n_rise> is never used or assigned.
WARNING:Xst:1780 - Signal <n_fall> is never used or assigned.
    Register <risesig<0>> equivalent to <fallsig<0>> has been removed
    Found finite state machine <FSM_0> for signal <m2_state>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 28                                             |
    | Inputs             | 7                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | m2_reset                                       |
    | Power Up State     | m2_reset                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:741 - HDL ADVISOR - A 6-bit shift register was found for signal <q<6>> and currently occupies 6 logic cells (3 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:741 - HDL ADVISOR - A 4-bit shift register was found for signal <q<19>> and currently occupies 4 logic cells (2 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
    Found 1-bit tristate buffer for signal <ps2_clk>.
    Found 1-bit tristate buffer for signal <ps2_data>.
    Found 1-bit register for signal <right_button>.
    Found 1-bit register for signal <left_button>.
    Found 10-bit register for signal <mousex>.
    Found 10-bit register for signal <mousey>.
    Found 10-bit adder for signal <$n0032> created at line 270.
    Found 10-bit adder for signal <$n0048> created at line 287.