bin2bcd7.vhd

来自「这是非常好的vhdl例子」· VHDL 代码 · 共 59 行

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:57:32 09/22/2006 
-- Design Name: 
-- Module Name:    bin2bcd7 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bin2bcd7 is
    Port ( bin_in : in  STD_LOGIC_VECTOR (3 downto 0);
           bcd7_out : out  STD_LOGIC_VECTOR (6 downto 0));
end bin2bcd7;

architecture Behavioral of bin2bcd7 is

begin
with bin_in SELect
bcd7_out<=
"1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"0001000"when"1010",
"0000011"when"1011",
"1000110"when"1100",
"0100001"when"1101",
"0000110"when"1110",
"0001110"when"1111",
"1000000"when others;

end Behavioral;