sn7448.vhd

这是非常好的vhdl例子

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:05:17 09/12/2006 
-- Design Name: 
-- Module Name:    SN7448 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the  following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SN7448 is
  port(lt,rbi:std_logic;
  datain:in std_logic_vector(3 downto 0);
  rbo_bi:inout std_logic;
  dataout:out std_logic_vector(7 downto 0););
end SN7448;

architecture Behavioral of SN7448 is
signal dataout_1:std_logic_vector(7 downto 0);

begin
  rbo_bi<=not(datain(0)and datain(1)and datain(2)and datain(3)and lt and(not rbi));
  process(datain,lt,rbi,rbo_bi)
  begin
  if(lt='1')then
  if(rbo_bi='1')then
    case datain is
	 when "0000"=>data_out1<="00111111";
	 when "0001"=>data_out1<="00000110";
	 when "0010"=>data_out1<="01011011";
	 when "0011"=>data_out1<="01001111";
	 when "0100"=>data_out1<="01100110";
	 when "0101"=>data_out1<="01101101";
	 when "0110"=>data_out1<="01111101";
	 when "0111"=>data_out1<="00000111";
	 when "1000"=>data_out1<="01111111";
	 when "1001"=>data_out1<="01101111";
	 when "1010"=>data_out1<="01110111";
	 when "1011"=>data_out1<="01111100";
	 when "1100"=>data_out1<="00111001";
	 when "1101"=>data_out1<="10011110";
	 when "1110"=>data_out1<="01111001";
	 when "1111"=>data_out1<="01110001";
	 when others=>data_out1<="00000000";
	 end case;
if(rbi='0' and dataout_1="00111111")then
   dataout<="00000000";
else 
             dataout<=dataout_1;
end if;
else 
dataout<="0000000";
end if;
else
dataout<="11111111";				 
end if;
end process;

end Behavioral;