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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file e:/work/coreban/submusic/top.vhd in Library work.Entity <musicdec> (Architecture <Behavioral>) compiled.Entity <top> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <top> (Architecture <Behavioral>).Entity <top> analyzed. Unit <top> generated.Analyzing Entity <musicdec> (Architecture <behavioral>).Entity <musicdec> analyzed. Unit <musicdec> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <musicdec>. Related source file is e:/work/coreban/submusic/top.vhd. Found 32x10-bit ROM for signal <$n0000>. Summary: inferred 1 ROM(s).Unit <musicdec> synthesized.Synthesizing Unit <top>. Related source file is e:/work/coreban/submusic/top.vhd. Found 256x8-bit ROM for signal <$n0014>. Found 448x8-bit ROM for signal <$n0015> created at line 259. Found 496x8-bit ROM for signal <$n0016> created at line 268. Found finite state machine <FSM_0> for signal <prestate>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 8 | | Inputs | 3 | | Outputs | 3 | | Clock | musicclk (rising_edge) | | Power Up State | idle | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 9-bit adder for signal <$n0040> created at line 255. Found 9-bit adder for signal <$n0042> created at line 263. Found 9-bit adder for signal <$n0044> created at line 272. Found 24-bit up accumulator for signal <addr>. Found 9-bit register for signal <codeaddr1>. Found 9-bit register for signal <codeaddr2>. Found 9-bit register for signal <codeaddr3>. Found 25-bit up counter for signal <divclk_counter>. Found 1-bit register for signal <musicclk>. Found 32-bit register for signal <musickeyshiftbuf>. Found 2-bit up counter for signal <musicno>. Found 8-bit register for signal <tonecode>. Summary: inferred 1 Finite State Machine(s). inferred 3 ROM(s). inferred 2 Counter(s). inferred 1 Accumulator(s). inferred 68 D-type flip-flop(s). inferred 3 Adder/Subtracter(s).Unit <top> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Selecting encoding for FSM_0 ...Optimizing FSM <FSM_0> on signal <prestate> with one-hot encoding.Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 1# ROMs : 4 496x8-bit ROM : 1 448x8-bit ROM : 1 256x8-bit ROM : 1 32x10-bit ROM : 1# Adders/Subtractors : 3 9-bit adder : 3# Counters : 2 25-bit up counter : 1 2-bit up counter : 1# Accumulators : 1 24-bit up accumulator : 1# Registers : 40 9-bit register : 3 8-bit register : 1 1-bit register : 36==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <tonecode_7> (without init value) is constant in block <top>.WARNING:Xst:1710 - FF/Latch <tonecode_4> (without init value) is constant in block <top>.WARNING:Xst:1710 - FF/Latch <tonecode_5> (without init value) is constant in block <top>.WARNING:Xst:1710 - FF/Latch <tonecode_6> (without init value) is constant in block <top>.Optimizing unit <top> ...Optimizing unit <musicdec> ...Loading device for application Xst from file '3s200.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 14.FlipFlop codeaddr3_5 has been replicated 1 time(s)FlipFlop codeaddr2_1 has been replicated 2 time(s)FlipFlop codeaddr3_2 has been replicated 2 time(s)FlipFlop codeaddr2_0 has been replicated 1 time(s)FlipFlop codeaddr3_3 has been replicated 2 time(s)FlipFlop codeaddr2_4 has been replicated 2 time(s)FlipFlop codeaddr3_4 has been replicated 2 time(s)FlipFlop codeaddr2_3 has been replicated 3 time(s)FlipFlop codeaddr2_2 has been replicated 3 time(s)FlipFlop codeaddr2_5 has been replicated 1 time(s)FlipFlop codeaddr2_3 has been replicated 1 time(s)FlipFlop codeaddr2_4 has been replicated 1 time(s)FlipFlop codeaddr1_3 has been replicated 1 time(s)FlipFlop codeaddr1_4 has been replicated 1 time(s)FlipFlop codeaddr3_3 has been replicated 1 time(s)=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200pq208-4 Number of Slices: 266 out of 1920 13% Number of Slice Flip Flops: 142 out of 3840 3% Number of 4 input LUTs: 383 out of 3840 9% Number of bonded IOBs: 8 out of 141 5% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+musicclk:Q | NONE | 58 |sysclk | BUFGP | 84 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 2.473ns (Maximum Frequency: 404.367MHz) Minimum input arrival time before clock: 4.221ns Maximum output required time after clock: 6.157ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd e:\work\coreban\submusic/_ngo -uctop.ucf -p xc3s200-pq208-4 top.ngc top.ngd Reading NGO file "e:/work/coreban/submusic/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 41872 kilobytesWriting NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "3s200pq208-4".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 9Logic Utilization: Number of Slice Flip Flops: 142 out of 3,840 3% Number of 4 input LUTs: 296 out of 3,840 7%Logic Distribution: Number of occupied Slices: 294 out of 1,920 15% Number of Slices containing only related logic: 294 out of 294 100% Number of Slices containing unrelated logic: 0 out of 294 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 383 out of 3,840 9% Number used as logic: 296 Number used as a route-thru: 87 Number of bonded IOBs: 9 out of 141 6% Number of GCLKs: 1 out of 8 12%Total equivalent gate count for design: 4,193Additional JTAG gate count for IOBs: 432Peak Memory Usage: 73 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "top_map.mrp" for details.Completed process "Map".Mapping Module top . . .
MAP command line:
map -intstyle ise -p xc3s200-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf
Mapping Module top: DONE
Started process "Place & Route".Constraints file: top.pcfLoading device database for application Par from file "top_map.ncd". "top" is an NCD, version 2.38, device xc3s200, package pq208, speed -4Loading device for application Par from file '3s200.nph' in environmentD:/Xilinx.Device speed data version: ADVANCED 1.29 2003-12-13.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External IOBs 9 out of 141 6% Number of LOCed External IOBs 9 out of 9 100% Number of Slices 294 out of 2880 10% Number of SLICEMs 76 out of 960 7% Number of BUFGMUXs 1 out of 8 12%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:989aa7) REAL time: 0 secs .Phase 3.8...............................................................Phase 3.8 (Checksum:99e124) REAL time: 2 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.18Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs Writing design to file top.ncd.Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 2 secs Phase 1: 1701 unrouted; REAL time: 2 secs Phase 2: 1589 unrouted; REAL time: 3 secs Phase 3: 525 unrouted; REAL time: 3 secs Phase 4: 0 unrouted; REAL time: 4 secs Total REAL time to Router completion: 4 secs Total CPU time to Router completion: 3 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+| sysclk_BUFGP | BUFGMUX1| No | 45 | 0.004 | 0.589 |+-------------------------+----------+------+------+------------+-------------+| musicclk | Local | | 35 | 0.554 | 2.966 |+-------------------------+----------+------+------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 4 secs Peak Memory Usage: 61 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file top.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Sat Oct 23 10:52:41 2004--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module top . . .
PAR command line: par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf
PAR completed successfully
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
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