top.par

来自「这是非常好的vhdl例子」· PAR 代码 · 共 128 行

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

EESTD::  Thu Dec 02 09:36:58 2004


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd
top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolved that IOB <spkout0> must be placed at site P3.
Resolved that IOB <spkout1> must be placed at site P4.
Resolved that IOB <sysclk> must be placed at site P80.
Resolved that IOB <musickey1> must be placed at site P45.
Resolved that IOB <tonekey1<0>> must be placed at site P37.
Resolved that IOB <tonekey1<1>> must be placed at site P39.
Resolved that IOB <tonekey1<2>> must be placed at site P40.
Resolved that IOB <tonekey1<3>> must be placed at site P42.
Resolved that IOB <tonekey1<4>> must be placed at site P43.


Device utilization summary:

   Number of External IOBs             9 out of 141     6%
      Number of LOCed External IOBs    9 out of 9     100%

   Number of Slices                  294 out of 5376    5%
      Number of SLICEMs               76 out of 1792    4%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989aa7) REAL time: 2 secs 

.
Phase 3.8
.......................
Phase 3.8 (Checksum:99e421) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1701 unrouted;       REAL time: 3 secs 

Phase 2: 1589 unrouted;       REAL time: 4 secs 

Phase 3: 463 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|      sysclk_BUFGP       |  BUFGMUX1| No   |   45 |  0.031     |  0.615      |
+-------------------------+----------+------+------+------------+-------------+
|          musicclk       |   Local  |      |   35 |  0.441     |  2.836      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 141


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.935
   The MAXIMUM PIN DELAY IS:                               3.147
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.389

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         932         684          83           2           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.