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这是非常好的vhdl例子

   Mrom__n0016__net246)
   	LUT symbol "Mrom__n0016_inst_lut4_1851" (Output Signal =
   Mrom__n0016_inst_lut4_1851/O)
   There is more than one MUXF6.
   Failure 2:  Unable to combine the following symbols into a single slice.
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_126" (Output Signal =
   Mrom__n0016__net273)
   	LUT symbol "Mrom__n0016_inst_mux_f5_1261" (Output Signal =
   Mrom__n0016_inst_mux_f5_1261/O)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_113" (Output Signal =
   Mrom__n0016__net243)
   	LUT symbol "Mrom__n0016_inst_mux_f5_1131" (Output Signal =
   Mrom__n0016_inst_mux_f5_1131/O)
   There is more than one F5MUX.
   Failure 3:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016__net278)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_128" (Output Signal =
   Mrom__n0016__net277)
   	LUT symbol "Mrom__n0016_inst_lut4_2141" (Output Signal =
   Mrom__n0016_inst_lut4_2141/O)
   	LUT symbol "Mrom__n0016_inst_lut4_2151" (Output Signal =
   Mrom__n0016_inst_lut4_2151/O)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_61" (Output Signal =
   Mrom__n0016__net248)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_116" (Output Signal =
   Mrom__n0016__net247)
   	LUT symbol "Mrom__n0016_inst_lut4_1861" (Output Signal =
   Mrom__n0016_inst_lut4_1861/O)
   	LUT symbol "Mrom__n0016_inst_lut4_1871" (Output Signal =
   Mrom__n0016_inst_lut4_1871/O)
   There is more than one MUXF6.
   Failure 4:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_67" (Output Signal =
   Mrom__n0016__net275)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_127" (Output Signal =
   Mrom__n0016__net274)
   	LUT symbol "Mrom__n0016_inst_lut4_2111" (Output Signal =
   Mrom__n0016_inst_lut4_2111/O)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_60" (Output Signal =
   Mrom__n0016__net245)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_114" (Output Signal =
   Mrom__n0016__net244)
   	LUT symbol "Mrom__n0016_inst_lut4_1841" (Output Signal =
   Mrom__n0016_inst_lut4_1841/O)
   There is more than one MUXF6.
   Failure 5:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net285)
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_35/MUXF6.I1/F5.I0)
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net255)
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_31/MUXF6.I1/F5.I0)
   	LUT symbol "Mrom__n0016_inst_lut2_111" (Output Signal = Mrom__n0016__net284)
   There is more than one MUXF6.
   Failure 6:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f8_19" (Output Signal =
   Mrom__n0016__net286)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_129" (Output Signal =
   Mrom__n0016__net280)
   	LUT symbol "Mrom__n0016_inst_lut4_2171" (Output Signal =
   Mrom__n0016_inst_lut4_2171/O)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f8_17" (Output Signal =
   Mrom__n0016__net256)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_117" (Output Signal =
   Mrom__n0016__net250)
   	LUT symbol "Mrom__n0016_inst_lut4_1881" (Output Signal =
   Mrom__n0016_inst_lut4_1881/O)
   There is more than one MUXF6.
   Failure 7:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016_inst_mux_f7_35/F6.I1)
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016_inst_mux_f7_31/F6.I1)
   There is more than one MUXF6.
   Failure 8:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016__net282)
   	MUXF5 symbol "MUXF5.I1" (Output Signal = Mrom__n0016_inst_mux_f6_69/F5.I1)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_62" (Output Signal =
   Mrom__n0016__net252)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_118" (Output Signal =
   Mrom__n0016__net251)
   	LUT symbol "Mrom__n0016_inst_lut4_1901" (Output Signal =
   Mrom__n0016_inst_lut4_1901/O)
   There is more than one MUXF6  The design will exhibit suboptimal timing.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "sysclk_BUFGP" (output signal=sysclk_BUFGP)

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| musickey1                          | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| spkout0                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| spkout1                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| sysclk                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| tonekey1<0>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| tonekey1<1>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| tonekey1<2>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| tonekey1<3>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| tonekey1<4>                        | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 9
Number of Equivalent Gates for Design = 4,193
Number of RPM Macros = 0
Number of Hard Macros = 0
DCIRESETs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DCMs = 0
GCLKs = 1
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 81
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 0
Unbonded IOBs = 0
Bonded IOBs = 9
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFXs = 284
MULTANDs = 0
4 input LUTs used as Route-Thrus = 87
4 input LUTs = 296
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 81
Slice Flip Flops = 142
SliceMs = 76
SliceLs = 218
Slices = 294
Number of LUT signals with 4 loads = 0
Number of LUT signals with 3 loads = 3
Number of LUT signals with 2 loads = 17
Number of LUT signals with 1 load = 267
NGM Average fanout of LUT = 1.54
NGM Maximum fanout of LUT = 26
NGM Average fanin for LUT = 3.0034
Number of LUT symbols = 296
Number of IPAD symbols = 7
Number of IBUF symbols = 7