top.mrp

这是非常好的vhdl例子

Release 6.2i Map G.28
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf 
Target Device  : x3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.16.8.1 $
Mapped Date    : Thu Dec 02 09:36:53 2004

Design Summary
--------------
Number of errors:      0
Number of warnings:    9
Logic Utilization:
  Number of Slice Flip Flops:         142 out of   7,168    1%
  Number of 4 input LUTs:             296 out of   7,168    4%
Logic Distribution:
  Number of occupied Slices:                          294 out of   3,584    8%
    Number of Slices containing only related logic:     294 out of     294  100%
    Number of Slices containing unrelated logic:          0 out of     294    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            383 out of   7,168    5%
  Number used as logic:                296
  Number used as a route-thru:          87
  Number of bonded IOBs:                9 out of     141    6%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  4,193
Additional JTAG gate count for IOBs:  432
Peak Memory Usage:  77 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:51 - Pin I1 of MUXF6 symbol
   "Mrom__n0014_inst_mux_f7_3/MUXF6.I1/MUXF6" (output
   signal=Mrom__n0014_inst_mux_f7_3/F6.I1) is not connected.
WARNING:LIT:51 - Pin I1 of MUXF6 symbol
   "Mrom__n0014_inst_mux_f7_4/MUXF6.I0/MUXF6" (output
   signal=Mrom__n0014_inst_mux_f7_4/F6.I0) is not connected.
WARNING:LIT:51 - Pin I1 of MUXF6 symbol
   "Mrom__n0016_inst_mux_f7_35/MUXF6.I1/MUXF6" (output
   signal=Mrom__n0016_inst_mux_f7_35/F6.I1) is not connected.
WARNING:LIT:51 - Pin I1 of MUXF6 symbol
   "Mrom__n0016_inst_mux_f7_23/MUXF6.I1/MUXF6" (output
   signal=Mrom__n0016_inst_mux_f7_23/F6.I1) is not connected.
WARNING:LIT:51 - Pin I1 of MUXF6 symbol
   "Mrom__n0016_inst_mux_f7_27/MUXF6.I1/MUXF6" (output
   signal=Mrom__n0016_inst_mux_f7_27/F6.I1) is not connected.
WARNING:LIT:51 - Pin I1 of MUXF6 symbol
   "Mrom__n0016_inst_mux_f7_31/MUXF6.I1/MUXF6" (output
   signal=Mrom__n0016_inst_mux_f7_31/F6.I1) is not connected.
WARNING:LIT:53 - There are 6 pin connection warnings.
WARNING:Pack:266 - The function generator Mrom__n0016_inst_lut2_111 failed to
   merge with F5 multiplexer MUXF5.I0.  Unable to resolve the conflicts between
   two or more collections of symbols which have restrictive placement or
   routing requirements.  The original symbols are:
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_23/MUXF6.I1/F5.I0)
   	LUT symbol "Mrom__n0016_inst_lut2_111" (Output Signal = Mrom__n0016__net284)
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net195)
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net255)
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_31/MUXF6.I1/F5.I0)
   Failure 1:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f7_22" (Output Signal =
   Mrom__n0016__net189)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_89" (Output Signal =
   Mrom__n0016__net186)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f7_30" (Output Signal =
   Mrom__n0016__net249)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_115" (Output Signal =
   Mrom__n0016__net246)
   	LUT symbol "Mrom__n0016_inst_lut4_1851" (Output Signal =
   Mrom__n0016_inst_lut4_1851/O)
   There is more than one MUXF6.
   Failure 2:  Unable to combine the following symbols into a single slice.
   	MUXF5 symbol "MUXF5.I0" (Output Signal = Mrom__n0016_inst_mux_f6_46/F5.I0)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_113" (Output Signal =
   Mrom__n0016__net243)
   	LUT symbol "Mrom__n0016_inst_mux_f5_1131" (Output Signal =
   Mrom__n0016_inst_mux_f5_1131/O)
   There is more than one F5MUX.
   Failure 3:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_47" (Output Signal =
   Mrom__n0016__net188)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_90" (Output Signal =
   Mrom__n0016__net187)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_61" (Output Signal =
   Mrom__n0016__net248)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_116" (Output Signal =
   Mrom__n0016__net247)
   	LUT symbol "Mrom__n0016_inst_lut4_1861" (Output Signal =
   Mrom__n0016_inst_lut4_1861/O)
   	LUT symbol "Mrom__n0016_inst_lut4_1871" (Output Signal =
   Mrom__n0016_inst_lut4_1871/O)
   There is more than one MUXF6.
   Failure 4:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016__net185)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_88" (Output Signal =
   Mrom__n0016__net184)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_60" (Output Signal =
   Mrom__n0016__net245)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_114" (Output Signal =
   Mrom__n0016__net244)
   	LUT symbol "Mrom__n0016_inst_lut4_1841" (Output Signal =
   Mrom__n0016_inst_lut4_1841/O)
   There is more than one MUXF6.
   Failure 5:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net195)
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_23/MUXF6.I1/F5.I0)
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net255)
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_31/MUXF6.I1/F5.I0)
   	LUT symbol "Mrom__n0016_inst_lut2_111" (Output Signal = Mrom__n0016__net284)
   There is more than one MUXF6.
   Failure 6:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f8_13" (Output Signal =
   Mrom__n0016__net196)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_91" (Output Signal =
   Mrom__n0016__net190)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f8_17" (Output Signal =
   Mrom__n0016__net256)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_117" (Output Signal =
   Mrom__n0016__net250)
   	LUT symbol "Mrom__n0016_inst_lut4_1881" (Output Signal =
   Mrom__n0016_inst_lut4_1881/O)
   There is more than one MUXF6.
   Failure 7:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016_inst_mux_f7_23/F6.I1)
   	MUXF6 symbol "MUXF6" (Output Signal = Mrom__n0016_inst_mux_f7_31/F6.I1)
   There is more than one MUXF6.
   Failure 8:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_48" (Output Signal =
   Mrom__n0016__net192)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_92" (Output Signal =
   Mrom__n0016__net191)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f6_62" (Output Signal =
   Mrom__n0016__net252)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_118" (Output Signal =
   Mrom__n0016__net251)
   	LUT symbol "Mrom__n0016_inst_lut4_1901" (Output Signal =
   Mrom__n0016_inst_lut4_1901/O)
   There is more than one MUXF6.  The design will exhibit suboptimal timing.
WARNING:Pack:266 - The function generator Mrom__n0016_inst_lut2_111 failed to
   merge with F5 multiplexer MUXF5.I0.  Unable to resolve the conflicts between
   two or more collections of symbols which have restrictive placement or
   routing requirements.  The original symbols are:
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_35/MUXF6.I1/F5.I0)
   	LUT symbol "Mrom__n0016_inst_lut2_111" (Output Signal = Mrom__n0016__net284)
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net285)
   	MUXF6 symbol "MUXF7" (Output Signal = Mrom__n0016__net255)
   	MUXF5 symbol "MUXF5.I0" (Output Signal =
   Mrom__n0016_inst_mux_f7_31/MUXF6.I1/F5.I0)
   Failure 1:  Unable to combine the following symbols into a single slice.
   	MUXF6 symbol "Mrom__n0016_inst_mux_f7_34" (Output Signal =
   Mrom__n0016__net279)
   	MUXF5 symbol "MUXF5.I0" (Output Signal = Mrom__n0016_inst_mux_f6_68/F5.I0)
   	MUXF6 symbol "Mrom__n0016_inst_mux_f7_30" (Output Signal =
   Mrom__n0016__net249)
   	MUXF5 symbol "Mrom__n0016_inst_mux_f5_115" (Output Signal =