top.syr

这是非常好的vhdl例子

FlipFlop codeaddr2_5 has been replicated 1 time(s)
FlipFlop codeaddr2_3 has been replicated 1 time(s)
FlipFlop codeaddr2_4 has been replicated 1 time(s)
FlipFlop codeaddr1_3 has been replicated 1 time(s)
FlipFlop codeaddr1_4 has been replicated 1 time(s)
FlipFlop codeaddr3_3 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 9

Macro Statistics :
# ROMs                             : 4
#      256x8-bit ROM               : 1
#      32x10-bit ROM               : 1
#      448x8-bit ROM               : 1
#      496x8-bit ROM               : 1
# Registers                        : 40
#      1-bit register              : 33
#      24-bit register             : 1
#      25-bit register             : 2
#      8-bit register              : 1
#      9-bit register              : 3
# Adders/Subtractors               : 6
#      24-bit adder                : 1
#      25-bit adder                : 2
#      9-bit adder                 : 3

Cell Usage :
# BELS                             : 785
#      GND                         : 1
#      LUT1                        : 96
#      LUT1_D                      : 1
#      LUT1_L                      : 13
#      LUT2                        : 14
#      LUT2_L                      : 64
#      LUT3                        : 17
#      LUT3_D                      : 2
#      LUT3_L                      : 51
#      LUT4                        : 60
#      LUT4_D                      : 2
#      LUT4_L                      : 63
#      MUXCY                       : 71
#      MUXF5                       : 132
#      MUXF6                       : 70
#      MUXF7                       : 36
#      MUXF8                       : 20
#      VCC                         : 1
#      XORCY                       : 71
# FlipFlops/Latches                : 142
#      FD                          : 109
#      FDE                         : 3
#      FDR                         : 26
#      FDS                         : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 8
#      IBUF                        : 6
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     266  out of   3584     7%  
 Number of Slice Flip Flops:           142  out of   7168     1%  
 Number of 4 input LUTs:               383  out of   7168     5%  
 Number of bonded IOBs:                  8  out of    141     5%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
musicclk:Q                         | NONE                   | 58    |
sysclk                             | BUFGP                  | 84    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.473ns (Maximum Frequency: 404.367MHz)
   Minimum input arrival time before clock: 4.221ns
   Maximum output required time after clock: 6.157ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'musicclk:Q'
Delay:               2.473ns (Levels of Logic = 4)
  Source:            codeaddr3_4 (FF)
  Destination:       codeaddr3_7 (FF)
  Source Clock:      musicclk:Q rising
  Destination Clock: musicclk:Q rising

  Data Path: codeaddr3_4 to codeaddr3_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              19   0.000   1.102  codeaddr3_4 (codeaddr3_4)
     LUT3:I1->O            1   0.000   0.240  Ker944324 (CHOICE46)
     LUT3_L:I1->LO         1   0.000   0.100  Ker944327 (CHOICE47)
     LUT3:I2->O           17   0.000   1.031  Ker944355 (N9445)
     LUT4_L:I3->LO         1   0.000   0.000  _n0028<7>1 (_n0028<7>)
     FD:D                      0.000          codeaddr3_7
    ----------------------------------------
    Total                      2.473ns (0.000ns logic, 2.473ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'sysclk'
Delay:               2.165ns (Levels of Logic = 4)
  Source:            divclk_counter_19 (FF)
  Destination:       musicclk (FF)
  Source Clock:      sysclk rising
  Destination Clock: sysclk rising

  Data Path: divclk_counter_19 to musicclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.000   0.465  divclk_counter_19 (divclk_counter_19)
     LUT4:I0->O            1   0.000   0.240  _n002244 (CHOICE204)
     LUT4_L:I1->LO         1   0.000   0.100  _n002283_SW0 (N11750)
     LUT4:I3->O            2   0.000   0.465  _n002283 (CHOICE217)
     LUT3:I2->O           13   0.000   0.895  _n002298 (_n0022)
     FDR:R                     0.000          divclk_counter_16
    ----------------------------------------
    Total                      2.165ns (0.000ns logic, 2.165ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'musicclk:Q'
Offset:              4.221ns (Levels of Logic = 5)
  Source:            tonekey1<1> (PAD)
  Destination:       codeaddr1_8 (FF)
  Destination Clock: musicclk:Q rising

  Data Path: tonekey1<1> to codeaddr1_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.641   0.658  tonekey1_1_IBUF (tonekey1_1_IBUF)
     LUT2:I0->O            3   0.000   0.577  Ker94771 (N9479)
     LUT4:I0->O           17   0.000   1.031  _n00341 (_n0034)
     LUT4_D:I2->O         25   0.000   1.314  Ker93451 (N9347)
     LUT4_L:I1->LO         1   0.000   0.000  _n0027<3>1_1 (N11809)
     FD:D                      0.000          codeaddr2_3_1
    ----------------------------------------
    Total                      4.221ns (0.641ns logic, 3.580ns route)
                                       (15.2% logic, 84.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'sysclk'
Offset:              1.329ns (Levels of Logic = 1)
  Source:            musickey1 (PAD)
  Destination:       musickeyshiftbuf_31 (FF)
  Destination Clock: sysclk rising

  Data Path: musickey1 to musickeyshiftbuf_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   0.641   0.688  musickey1_IBUF (musickey1_IBUF)
     FDR:R                     0.000          musickeyshiftbuf_31
    ----------------------------------------
    Total                      1.329ns (0.641ns logic, 0.688ns route)
                                       (48.2% logic, 51.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'sysclk'
Offset:              6.157ns (Levels of Logic = 1)
  Source:            addr_23 (FF)
  Destination:       spkout0 (PAD)
  Source Clock:      sysclk rising

  Data Path: addr_23 to spkout0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.000   0.577  addr_23 (addr_23)
     OBUF:I->O                 5.580          spkout0_OBUF (spkout0)
    ----------------------------------------
    Total                      6.157ns (5.580ns logic, 0.577ns route)
                                       (90.6% logic, 9.4% route)

=========================================================================
CPU : 19.13 / 21.57 s | Elapsed : 19.00 / 22.00 s
 
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Total memory usage is 75956 kilobytes