top.syr

这是非常好的vhdl例子

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.31 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.31 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/MUSICDEC is now defined in a different file: was e:/work/coreban/submusic/top.vhd, now is E:/work/digital_sward/sub_DEMO/submusic/top.vhd
WARNING:HDLParsers:3215 - Unit work/MUSICDEC/BEHAVIORAL is now defined in a different file: was e:/work/coreban/submusic/top.vhd, now is E:/work/digital_sward/sub_DEMO/submusic/top.vhd
WARNING:HDLParsers:3215 - Unit work/TOP is now defined in a different file: was e:/work/coreban/submusic/top.vhd, now is E:/work/digital_sward/sub_DEMO/submusic/top.vhd
WARNING:HDLParsers:3215 - Unit work/TOP/BEHAVIORAL is now defined in a different file: was e:/work/coreban/submusic/top.vhd, now is E:/work/digital_sward/sub_DEMO/submusic/top.vhd
Compiling vhdl file E:/work/digital_sward/sub_DEMO/submusic/top.vhd in Library work.
Architecture behavioral of Entity musicdec is up to date.
Architecture behavioral of Entity top is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <musicdec> (Architecture <behavioral>).
Entity <musicdec> analyzed. Unit <musicdec> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <musicdec>.
    Related source file is E:/work/digital_sward/sub_DEMO/submusic/top.vhd.
    Found 32x10-bit ROM for signal <$n0000>.
    Summary:
	inferred   1 ROM(s).
Unit <musicdec> synthesized.


Synthesizing Unit <top>.
    Related source file is E:/work/digital_sward/sub_DEMO/submusic/top.vhd.
    Found 256x8-bit ROM for signal <$n0014>.
    Found 448x8-bit ROM for signal <$n0015> created at line 259.
    Found 496x8-bit ROM for signal <$n0016> created at line 268.
    Found finite state machine <FSM_0> for signal <prestate>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 8                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | musicclk (rising_edge)                         |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <$n0040> created at line 255.
    Found 9-bit adder for signal <$n0042> created at line 263.
    Found 9-bit adder for signal <$n0044> created at line 272.
    Found 24-bit up accumulator for signal <addr>.
    Found 9-bit register for signal <codeaddr1>.
    Found 9-bit register for signal <codeaddr2>.
    Found 9-bit register for signal <codeaddr3>.
    Found 25-bit up counter for signal <divclk_counter>.
    Found 1-bit register for signal <musicclk>.
    Found 32-bit register for signal <musickeyshiftbuf>.
    Found 2-bit up counter for signal <musicno>.
    Found 8-bit register for signal <tonecode>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 ROM(s).
	inferred   2 Counter(s).
	inferred   1 Accumulator(s).
	inferred  68 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <prestate> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 4
 496x8-bit ROM                     : 1
 448x8-bit ROM                     : 1
 256x8-bit ROM                     : 1
 32x10-bit ROM                     : 1
# Adders/Subtractors               : 3
 9-bit adder                       : 3
# Counters                         : 2
 25-bit up counter                 : 1
 2-bit up counter                  : 1
# Accumulators                     : 1
 24-bit up accumulator             : 1
# Registers                        : 40
 9-bit register                    : 3
 8-bit register                    : 1
 1-bit register                    : 36

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <tonecode_7> (without init value) is constant in block <top>.
WARNING:Xst:1710 - FF/Latch  <tonecode_4> (without init value) is constant in block <top>.
WARNING:Xst:1710 - FF/Latch  <tonecode_5> (without init value) is constant in block <top>.
WARNING:Xst:1710 - FF/Latch  <tonecode_6> (without init value) is constant in block <top>.

Optimizing unit <top> ...

Optimizing unit <musicdec> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 7.
FlipFlop codeaddr3_5 has been replicated 1 time(s)
FlipFlop codeaddr2_1 has been replicated 2 time(s)
FlipFlop codeaddr3_2 has been replicated 2 time(s)
FlipFlop codeaddr2_0 has been replicated 1 time(s)
FlipFlop codeaddr3_3 has been replicated 2 time(s)
FlipFlop codeaddr2_4 has been replicated 2 time(s)
FlipFlop codeaddr3_4 has been replicated 2 time(s)
FlipFlop codeaddr2_3 has been replicated 3 time(s)
FlipFlop codeaddr2_2 has been replicated 3 time(s)