clock.par

这是非常好的vhdl例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

EESTD::  Thu Dec 02 09:21:37 2004


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd
clock.pcf 


Constraints file: clock.pcf

Loading device database for application Par from file "clock_map.ncd".
   "clock" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolved that IOB <en> must be placed at site P205.
Resolved that IOB <clk> must be placed at site P80.
Resolved that IOB <seg<0>> must be placed at site P16.
Resolved that IOB <seg<1>> must be placed at site P18.
Resolved that IOB <seg<2>> must be placed at site P13.
Resolved that IOB <seg<3>> must be placed at site P15.
Resolved that IOB <seg<4>> must be placed at site P9.
Resolved that IOB <a<0>> must be placed at site P20.
Resolved that IOB <seg<5>> must be placed at site P12.
Resolved that IOB <a<1>> must be placed at site P19.
Resolved that IOB <seg<6>> must be placed at site P11.
Resolved that IOB <a<2>> must be placed at site P22.
Resolved that IOB <seg<7>> must be placed at site P10.
Resolved that IOB <a<3>> must be placed at site P21.


Device utilization summary:

   Number of External IOBs            14 out of 141     9%
      Number of LOCed External IOBs   14 out of 14    100%

   Number of Slices                   70 out of 3584    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98978d) REAL time: 0 secs 

.
Phase 3.8
..
Phase 3.8 (Checksum:98eb0c) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file clock.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 429 unrouted;       REAL time: 2 secs 

Phase 2: 391 unrouted;       REAL time: 2 secs 

Phase 3: 132 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX1| No   |   25 |  0.006     |  0.590      |
+-------------------------+----------+------+------+------------+-------------+
|            divclk       |   Local  |      |    9 |  0.206     |  1.941      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 114


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.802
   The MAXIMUM PIN DELAY IS:                               2.221
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.714

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         304         118           7           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  67 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clock.ncd.


PAR done.