coregen.log

这是非常好的vhdl例子

# Xilinx CORE Generator 6.2i
# User = wukong
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\work\digital_sward\sub_DEMO\subseg\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\work\digital_sward\sub_DEMO\subseg
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\work\digital_sward\sub_DEMO\subseg
SETPROJECT .
Set current Project to E:\work\digital_sward\sub_DEMO\subseg
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1239
XIPCPJSENDCORES spartan3