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这是非常好的vhdl例子

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/work/coreban/subseg/top.vhd in Library work.
Entity <clock> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <Behavioral>).
INFO:Xst:1561 - e:/work/coreban/subseg/top.vhd line 91: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/work/coreban/subseg/top.vhd line 77: The following signals are missing in the process sensitivity list:
   SecSeg1, SecSeg2, MinSeg1, MinSeg2.
Entity <clock> analyzed. Unit <clock> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clock>.
    Related source file is e:/work/coreban/subseg/top.vhd.
    Found 16x8-bit ROM for signal <SecSeg1>.
    Found 16x8-bit ROM for signal <MinSeg1>.
    Found 8-bit 4-to-1 multiplexer for signal <seg>.
    Found 1-of-4 decoder for signal <a>.
    Found 28-bit comparator greatequal for signal <$n0005> created at line 30.
    Found 4-bit comparator greatequal for signal <$n0007> created at line 42.
    Found 4-bit comparator greatequal for signal <$n0027> created at line 44.
    Found 4-bit comparator greatequal for signal <$n0028> created at line 46.
    Found 4-bit comparator less for signal <$n0029> created at line 44.
    Found 4-bit comparator less for signal <$n0030> created at line 42.
    Found 4-bit comparator greater for signal <$n0031> created at line 48.
    Found 4-bit comparator less for signal <$n0032> created at line 46.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 4-bit up counter for signal <min_counter1>.
    Found 4-bit up counter for signal <min_counter2>.
    Found 23-bit up counter for signal <scan>.
    Found 4-bit up counter for signal <sec_counter1>.
    Found 4-bit up counter for signal <sec_counter2>.
    Summary:
	inferred   2 ROM(s).
	inferred   6 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x8-bit ROM                      : 2
# Counters                         : 6
 23-bit up counter                 : 1
 28-bit up counter                 : 1
 4-bit up counter                  : 4
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 8
 4-bit comparator greater          : 1
 4-bit comparator less             : 3
 4-bit comparator greatequal       : 3
 28-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <scan_21> is unconnected in block <clock>.
WARNING:Xst:1291 - FF/Latch <scan_22> is unconnected in block <clock>.
WARNING:Xst:1291 - FF/Latch <scan_19> is unconnected in block <clock>.
WARNING:Xst:1291 - FF/Latch <scan_20> is unconnected in block <clock>.

Optimizing unit <clock> ...
Loading device for application Xst from file '3s200.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clock, actual ratio is 4.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                      74  out of   1920     3%  
 Number of Slice Flip Flops:            64  out of   3840     1%  
 Number of 4 input LUTs:               139  out of   3840     3%  
 Number of bonded IOBs:                 13  out of    141     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 48    |
divclk:Q                           | NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.660ns (Maximum Frequency: 375.940MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.174ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\work\coreban\subseg/_ngo -uc top.ucf
-p xc3s200-pq208-4 clock.ngc clock.ngd 

Reading NGO file "e:/work/coreban/subseg/clock.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40848 kilobytes

Writing NGD file "clock.ngd" ...

Writing NGDBUILD log file "clock.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s200pq208-4".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          64 out of   3,840    1%
  Number of 4 input LUTs:              84 out of   3,840    2%
Logic Distribution:
  Number of occupied Slices:                           70 out of   1,920    3%
    Number of Slices containing only related logic:      70 out of      70  100%
    Number of Slices containing unrelated logic:          0 out of      70    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            134 out of   3,840    3%
  Number used as logic:                 84
  Number used as a route-thru:          50
  Number of bonded IOBs:               14 out of     141    9%
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  1,373
Additional JTAG gate count for IOBs:  672
Peak Memory Usage:  70 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clock_map.mrp" for details.
Completed process "Map".

Mapping Module clock . . .
MAP command line:
map -intstyle ise -p xc3s200-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o clock_map.ncd clock.ngd clock.pcf
Mapping Module clock: DONE



Started process "Place & Route".





Constraints file: clock.pcf

Loading device database for application Par from file "clock_map.ncd".
   "clock" is an NCD, version 2.38, device xc3s200, package pq208, speed -4
Loading device for application Par from file '3s200.nph' in environment
D:/Xilinx.
Device speed data version:  ADVANCED 1.29 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            14 out of 141     9%
      Number of LOCed External IOBs   14 out of 14    100%

   Number of Slices                   70 out of 1920    3%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98978d) REAL time: 0 secs 

.
Phase 3.8
..
Phase 3.8 (Checksum:98e53f) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file clock.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 429 unrouted;       REAL time: 2 secs 

Phase 2: 391 unrouted;       REAL time: 2 secs 

Phase 3: 115 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX1| No   |   25 |  0.007     |  0.592      |
+-------------------------+----------+------+------+------------+-------------+
|            divclk       |   Local  |      |    9 |  0.271     |  1.841      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  59 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clock.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Sat Oct 23 14:19:37 2004
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clock . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd clock.pcf
PAR completed successfully



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Started process "Generate Programming File".

Completed process "Generate Programming File".



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