clock.syr

这是非常好的vhdl例子

Top Level Output File Name         : clock
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# ROMs                             : 2
#      16x8-bit ROM                : 2
# Registers                        : 7
#      1-bit register              : 1
#      28-bit register             : 6
# Multiplexers                     : 1
#      8-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 6
#      28-bit adder                : 6
# Comparators                      : 8
#      28-bit comparator greatequal: 1
#      4-bit comparator greatequal : 3
#      4-bit comparator greater    : 1
#      4-bit comparator less       : 3

Cell Usage :
# BELS                             : 259
#      GND                         : 1
#      LUT1                        : 64
#      LUT2                        : 14
#      LUT2_L                      : 1
#      LUT3                        : 24
#      LUT4                        : 34
#      LUT4_D                      : 2
#      MUXCY                       : 65
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 45
# FlipFlops/Latches                : 64
#      FD                          : 19
#      FDE                         : 1
#      FDR                         : 32
#      FDRE                        : 12
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 13
#      OBUF                        : 13
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      74  out of   3584     2%  
 Number of Slice Flip Flops:            64  out of   7168     0%  
 Number of 4 input LUTs:               139  out of   7168     1%  
 Number of bonded IOBs:                 13  out of    141     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 48    |
divclk:Q                           | NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.660ns (Maximum Frequency: 375.940MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.174ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               1.895ns (Levels of Logic = 17)
  Source:            divcounter_11 (FF)
  Destination:       divcounter_26 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: divcounter_11 to divcounter_26
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.000   0.577  divcounter_11 (divcounter_11)
     LUT4:I0->O            1   0.000   0.000  Mcompar__n0005_inst_lut4_191 (Mcompar__n0005_inst_lut4_19)
     MUXCY:S->O            1   0.000   0.000  Mcompar__n0005_inst_cy_5 (Mcompar__n0005_inst_cy_5)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_6 (Mcompar__n0005_inst_cy_6)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_7 (Mcompar__n0005_inst_cy_7)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_8 (Mcompar__n0005_inst_cy_8)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_9 (Mcompar__n0005_inst_cy_9)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_10 (Mcompar__n0005_inst_cy_10)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_11 (Mcompar__n0005_inst_cy_11)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_12 (Mcompar__n0005_inst_cy_12)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_13 (Mcompar__n0005_inst_cy_13)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_14 (Mcompar__n0005_inst_cy_14)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_15 (Mcompar__n0005_inst_cy_15)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_16 (Mcompar__n0005_inst_cy_16)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_17 (Mcompar__n0005_inst_cy_17)
     MUXCY:CI->O           1   0.000   0.000  Mcompar__n0005_inst_cy_18 (Mcompar__n0005_inst_cy_18)
     MUXCY:CI->O          29   0.000   1.318  Mcompar__n0005_inst_cy_19 (_n0005)
     FDE:CE                    0.000          divclk
    ----------------------------------------
    Total                      1.895ns (0.000ns logic, 1.895ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'divclk:Q'
Delay:               2.660ns (Levels of Logic = 4)
  Source:            sec_counter2_0 (FF)
  Destination:       min_counter2_3 (FF)
  Source Clock:      divclk:Q rising
  Destination Clock: divclk:Q rising

  Data Path: sec_counter2_0 to min_counter2_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             9   0.000   0.777  sec_counter2_0 (sec_counter2_0)
     LUT4_D:I2->O          3   0.000   0.577  SecSeg2<3>1 (SecSeg2<3>)
     LUT2_L:I1->LO         1   0.000   0.100  Ker4744_SW0 (N6532)
     LUT4:I0->O            3   0.000   0.577  Ker4744 (N4746)
     LUT2:I1->O            4   0.000   0.629  _n00391 (_n0039)
     FDRE:CE                   0.000          min_counter2_0
    ----------------------------------------
    Total                      2.660ns (0.000ns logic, 2.660ns route)
                                       (0.0% logic, 100.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.957ns (Levels of Logic = 2)
  Source:            scan_17 (FF)
  Destination:       a<3> (PAD)
  Source Clock:      clk rising

  Data Path: scan_17 to a<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              20   0.000   1.137  scan_17 (scan_17)
     LUT3:I0->O            1   0.000   0.000  Mmux_seg_inst_lut3_31 (Mmux_seg__net4)
     MUXF5:I1->O           1   0.000   0.240  Mmux_seg_inst_mux_f5_1 (seg_1_OBUF)
     OBUF:I->O                 5.580          seg_1_OBUF (seg<1>)
    ----------------------------------------
    Total                      6.957ns (5.580ns logic, 1.377ns route)
                                       (80.2% logic, 19.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'divclk:Q'
Offset:              7.174ns (Levels of Logic = 4)
  Source:            sec_counter2_0 (FF)
  Destination:       seg<3> (PAD)
  Source Clock:      divclk:Q rising

  Data Path: sec_counter2_0 to seg<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             9   0.000   0.777  sec_counter2_0 (sec_counter2_0)
     LUT4_D:I2->O          3   0.000   0.577  SecSeg2<3>1 (SecSeg2<3>)
     LUT3:I2->O            1   0.000   0.000  Mmux_seg_inst_lut3_61 (Mmux_seg__net9)
     MUXF5:I0->O           1   0.000   0.240  Mmux_seg_inst_mux_f5_3 (seg_3_OBUF)
     OBUF:I->O                 5.580          seg_3_OBUF (seg<3>)
    ----------------------------------------
    Total                      7.174ns (5.580ns logic, 1.594ns route)
                                       (77.8% logic, 22.2% route)

=========================================================================
CPU : 19.70 / 21.15 s | Elapsed : 19.00 / 21.00 s
 
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Total memory usage is 72884 kilobytes