clock.syr

这是非常好的vhdl例子

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: clock.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : clock.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : clock
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : clock.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/CLOCK is now defined in a different file: was e:/work/coreban/subseg/top.vhd, now is E:/work/digital_sward/sub_DEMO/subseg/top.vhd
WARNING:HDLParsers:3215 - Unit work/CLOCK/BEHAVIORAL is now defined in a different file: was e:/work/coreban/subseg/top.vhd, now is E:/work/digital_sward/sub_DEMO/subseg/top.vhd
Compiling vhdl file E:/work/digital_sward/sub_DEMO/subseg/top.vhd in Library work.
Architecture behavioral of Entity clock is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <clock> (Architecture <behavioral>).
INFO:Xst:1561 - E:/work/digital_sward/sub_DEMO/subseg/top.vhd line 91: Mux is complete : default of case is discarded
WARNING:Xst:819 - E:/work/digital_sward/sub_DEMO/subseg/top.vhd line 77: The following signals are missing in the process sensitivity list:
   SecSeg1, SecSeg2, MinSeg1, MinSeg2.
Entity <clock> analyzed. Unit <clock> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clock>.
    Related source file is E:/work/digital_sward/sub_DEMO/subseg/top.vhd.
    Found 16x8-bit ROM for signal <SecSeg1>.
    Found 16x8-bit ROM for signal <MinSeg1>.
    Found 8-bit 4-to-1 multiplexer for signal <seg>.
    Found 1-of-4 decoder for signal <a>.
    Found 28-bit comparator greatequal for signal <$n0005> created at line 30.
    Found 4-bit comparator greatequal for signal <$n0007> created at line 42.
    Found 4-bit comparator greatequal for signal <$n0027> created at line 44.
    Found 4-bit comparator greatequal for signal <$n0028> created at line 46.
    Found 4-bit comparator less for signal <$n0029> created at line 44.
    Found 4-bit comparator less for signal <$n0030> created at line 42.
    Found 4-bit comparator greater for signal <$n0031> created at line 48.
    Found 4-bit comparator less for signal <$n0032> created at line 46.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 4-bit up counter for signal <min_counter1>.
    Found 4-bit up counter for signal <min_counter2>.
    Found 23-bit up counter for signal <scan>.
    Found 4-bit up counter for signal <sec_counter1>.
    Found 4-bit up counter for signal <sec_counter2>.
    Summary:
	inferred   2 ROM(s).
	inferred   6 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x8-bit ROM                      : 2
# Counters                         : 6
 23-bit up counter                 : 1
 28-bit up counter                 : 1
 4-bit up counter                  : 4
# Registers                        : 1
 1-bit register                    : 1
# Comparators                      : 8
 4-bit comparator greater          : 1
 4-bit comparator less             : 3
 4-bit comparator greatequal       : 3
 28-bit comparator greatequal      : 1
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <scan_21> is unconnected in block <clock>.
WARNING:Xst:1291 - FF/Latch <scan_22> is unconnected in block <clock>.
WARNING:Xst:1291 - FF/Latch <scan_19> is unconnected in block <clock>.
WARNING:Xst:1291 - FF/Latch <scan_20> is unconnected in block <clock>.

Optimizing unit <clock> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clock, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : clock.ngr