clock.twr

这是非常好的vhdl例子

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml clock clock.ncd -o
clock.twr clock.pcf


Design file:              clock.ncd
Physical constraint file: clock.pcf
Device,speed:             xc3s400,-4 (ADVANCED 1.29 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
a<0>        |   10.015(R)|clk_BUFGP         |   0.000|
a<1>        |   10.284(R)|clk_BUFGP         |   0.000|
a<2>        |    9.947(R)|clk_BUFGP         |   0.000|
a<3>        |    9.841(R)|clk_BUFGP         |   0.000|
seg<0>      |   10.522(R)|clk_BUFGP         |   0.000|
seg<1>      |   10.643(R)|clk_BUFGP         |   0.000|
seg<2>      |   10.884(R)|clk_BUFGP         |   0.000|
seg<3>      |   11.781(R)|clk_BUFGP         |   0.000|
seg<4>      |   11.110(R)|clk_BUFGP         |   0.000|
seg<5>      |   11.970(R)|clk_BUFGP         |   0.000|
seg<6>      |   11.020(R)|clk_BUFGP         |   0.000|
seg<7>      |   10.812(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.094|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Dec 02 09:21:42 2004
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Peak Memory Usage: 58 MB