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这是非常好的vhdl例子

net "clk"  loc=p80;
net a<0> loc=p20;
net a<1> loc=p19;
net a<2> loc=p22;
net a<3> loc=p21;
net seg<0> loc=p16;
net seg<1> loc=p18;
net seg<2> loc=p13;
net seg<3> loc=p15;
net seg<4> loc=p9;
net seg<5> loc=p12;
net seg<6> loc=p11;
net seg<7> loc=p10;	
net en loc=p205;