binarycounter.syr

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Release 8.1.03i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Reading design: BinaryCounter.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "BinaryCounter.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "BinaryCounter"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : BinaryCounter
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : BinaryCounter.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/vhdl/binarycounter/binarycouter.vhd" in Library work.
Architecture behavioral of Entity binarycounter is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <BinaryCounter> (Architecture <behavioral>).
Entity <BinaryCounter> analyzed. Unit <BinaryCounter> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <BinaryCounter>.
    Related source file is "E:/vhdl/binarycounter/binarycouter.vhd".
    Found 8-bit up counter for signal <counter>.
    Found 24-bit up counter for signal <tempcounter>.
    Summary:
	inferred   2 Counter(s).
Unit <BinaryCounter> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 24-bit up counter                                     : 1
 8-bit up counter                                      : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 24-bit up counter                                     : 1
 8-bit up counter                                      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment E:\Xilinx.

Optimizing unit <BinaryCounter> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block BinaryCounter, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : BinaryCounter.ngr
Top Level Output File Name         : BinaryCounter
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 10

Cell Usage :
# BELS                             : 90
#      GND                         : 1
#      INV                         : 9
#      LUT1_L                      : 23
#      LUT2                        : 1
#      LUT2_L                      : 3
#      LUT3                        : 1
#      LUT3_L                      : 1
#      LUT4                        : 2
#      LUT4_L                      : 2
#      MUXCY                       : 23
#      VCC                         : 1
#      XORCY                       : 23
# FlipFlops/Latches                : 32
#      FD                          : 32
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 9
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      18  out of   3584     0%  
 Number of Slice Flip Flops:            32  out of   7168     0%  
 Number of 4 input LUTs:                33  out of   7168     0%  
 Number of bonded IOBs:                 10  out of    141     7%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 24    |
tempcounter_23                     | NONE                   | 8     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.362ns (Maximum Frequency: 186.498MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.795ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.362ns (frequency: 186.498MHz)
  Total number of paths / destination ports: 300 / 24
-------------------------------------------------------------------------
Delay:               5.362ns (Levels of Logic = 24)
  Source:            tempcounter_1 (FF)
  Destination:       tempcounter_23 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: tempcounter_1 to tempcounter_23
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.720   1.140  tempcounter_1 (tempcounter_1)
     LUT1_L:I0->LO         1   0.551   0.000  tempcounter_1_rt (tempcounter_1_rt)
     MUXCY:S->O            1   0.500   0.000  BinaryCounter_Result<1>cy (BinaryCounter_Result<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<2>cy (BinaryCounter_Result<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<3>cy (BinaryCounter_Result<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<4>cy (BinaryCounter_Result<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<5>cy (BinaryCounter_Result<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<6>cy (BinaryCounter_Result<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<7>cy (BinaryCounter_Result<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<8>cy (BinaryCounter_Result<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<9>cy (BinaryCounter_Result<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<10>cy (BinaryCounter_Result<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<11>cy (BinaryCounter_Result<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<12>cy (BinaryCounter_Result<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<13>cy (BinaryCounter_Result<13>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<14>cy (BinaryCounter_Result<14>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<15>cy (BinaryCounter_Result<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<16>cy (BinaryCounter_Result<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<17>cy (BinaryCounter_Result<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<18>cy (BinaryCounter_Result<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<19>cy (BinaryCounter_Result<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<20>cy (BinaryCounter_Result<20>_cyo)
     MUXCY:CI->O           1   0.064   0.000  BinaryCounter_Result<21>cy (BinaryCounter_Result<21>_cyo)
     MUXCY:CI->O           0   0.064   0.000  BinaryCounter_Result<22>cy (BinaryCounter_Result<22>_cyo)
     XORCY:CI->O           1   0.904   0.000  BinaryCounter_Result<23>_xor (Result<23>)
     FD:D                      0.203          tempcounter_23
    ----------------------------------------
    Total                      5.362ns (4.222ns logic, 1.140ns route)
                                       (78.7% logic, 21.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'tempcounter_23'
  Clock period: 5.060ns (frequency: 197.628MHz)
  Total number of paths / destination ports: 36 / 8
-------------------------------------------------------------------------
Delay:               5.060ns (Levels of Logic = 3)
  Source:            counter_3 (FF)
  Destination:       counter_5 (FF)
  Source Clock:      tempcounter_23 rising
  Destination Clock: tempcounter_23 rising

  Data Path: counter_3 to counter_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.720   1.256  counter_3 (counter_3)
     LUT2_L:I0->LO         1   0.551   0.126  BinaryCounter_Result<4>1cy1_SW0 (N3)
     LUT4:I3->O            3   0.551   1.102  BinaryCounter_Result<4>1cy1 (BinaryCounter_Result<4>1_cyo)
     LUT2_L:I1->LO         1   0.551   0.000  BinaryCounter_Result<5>1_xor11 (Result<5>1)
     FD:D                      0.203          counter_5
    ----------------------------------------
    Total                      5.060ns (2.576ns logic, 2.484ns route)
                                       (50.9% logic, 49.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'tempcounter_23'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              8.795ns (Levels of Logic = 2)
  Source:            counter_0 (FF)
  Destination:       dout<0> (PAD)
  Source Clock:      tempcounter_23 rising

  Data Path: counter_0 to dout<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               6   0.720   1.003  counter_0 (counter_0)
     INV:I->O              2   0.551   0.877  dout<0>1_INV_0 (dout_0_OBUF)
     OBUF:I->O                 5.644          dout_0_OBUF (dout<0>)
    ----------------------------------------
    Total                      8.795ns (6.915ns logic, 1.880ns route)
                                       (78.6% logic, 21.4% route)

=========================================================================
CPU : 12.19 / 12.65 s | Elapsed : 12.00 / 12.00 s
 
--> 

Total memory usage is 128952 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)