binarycouter.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:10:32 10/07/2006 
-- Design Name: 
-- Module Name:    binarycouter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BinaryCounter is
Port ( clk : in std_logic;
ledce: out std_logic;
dout : out std_logic_vector(7 downto 0));
end BinaryCounter;
architecture Behavioral of BinaryCounter is
signal tempcounter:std_logic_vector(23 downto 0);
signal counterclk:std_logic;
signal counter:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
tempcounter<=tempcounter+'1';
end if;
end process;
counterclk<=tempcounter(23);
process(counterclk)
begin
if counterclk'event and counterclk='1' then
counter<=counter+'1';
end if;
end process;
dout<= not counter;
ledce<='0';
end Behavioral;