shift_register.vhd

我是VHDL的初学者

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

Entity shift_register is 
       port (
       Data_in: in std_logic_vector(7 downto 0);
       Data_out: out std_logic_vector(7 downto 0);
       Clk: in std_logic;
       Enable: in std_logic;
       Reset: in std_logic;
       Addr: in std_logic_vector(3 downto 0)
       );
End shift_register;




Architecture shift_register1 of shift_register is

type reg_array is array (15 downto 0) of std_logic_vector(7 downto 0);
Signal reg: reg_array;
 
begin 
    process (Clk,Reset,Enable)
    begin
    Data_out<=reg(conv_integer(unsigned(Addr)));
    If  Reset='1' then 
    	for k in reg_array'range loop
    		reg(k)<="00000000";
    			end loop;
    			
    	
    elsif (Clk'event and Clk='1')then
       	 if Enable='1' then
       		reg(0)<=Data_in;
       		for i in 15 downto 1 loop 
       			reg(i)<=reg(i-1);
       			
       		end loop;
       	      end if;
     
    End if;
    
       		
       
    
    
    End process;
    
End Architecture shift_register1;