test_bench.vhd

我是VHDL的初学者

entity testbench is
end;

------------------------------------------------------------------------
-- testbench for shift-register
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_1164.all;

architecture s_register of testbench is 
    component shift_register 
       port (
       Data_in: in std_logic_vector(7 downto 0);
       Data_out: out std_logic_vector(7 downto 0);
       Clk: in std_logic;
       Enable: in std_logic;
       Reset: in std_logic;
       Addr: in std_logic_vector(3 downto 0)
       );
    end component;

    signal Data_in    : std_logic_vector(7 downto 0);
    signal Data_out		 : std_logic_vector(7 downto 0);
    signal Clk        : std_logic:='1';
    signal Enable     : std_logic;
    signal Reset      : std_logic;
    signal Addr       : std_logic_vector(3 downto 0);
    
    type test_record_t is record
	
	Data_in    : std_logic_vector(7 downto 0);
	Data_out   : std_logic_vector(7 downto 0);
	Enable     : std_logic;
	Reset      : std_logic;
	Addr       : std_logic_vector(3 downto 0);
    end record;
    
    type test_array_t is array(positive range <>) of test_record_t;

    constant test_patterns : test_array_t := (
	(Data_in => "00000000",  Data_out=> "00000000", Enable => '1', Reset=>'1',Addr=>"0001"),
	(Data_in => "00000001",  Data_out=> "00000000", Enable => '1', Reset=>'0',Addr=>"0001"),
	(Data_in => "00000010",  Data_out=> "00000000",Enable => '1', Reset=>'0',Addr=>"0001"),
	(Data_in => "00000011",  Data_out=> "00000001",Enable => '1', Reset=>'0',Addr=>"0001")
	
    );

    --
    -- convert a std_logic value to a character
    --
    type stdlogic_to_char_t is array(std_logic) of character;
    constant to_char : stdlogic_to_char_t := (
	'U' => 'U',
	'X' => 'X',
	'0' => '0',
	'1' => '1',
	'Z' => 'Z',
	'W' => 'W',
	'L' => 'L',
	'H' => 'H',
	'-' => '-');

    --
    -- convert a std_logic_vector to a string
    --
    function to_string(inp : std_logic_vector)
    return string
    is
	alias vec : std_logic_vector(1 to inp'length) is inp;
	variable result : string(vec'range);
    begin
	for i in vec'range loop
	    result(i) := to_char(vec(i));
	end loop;
	return result;
    end;

begin
    -- instantiate the component
    uut: shift_register port map(Data_in => Data_in,
			 Data_out => Data_out,
			 Clk => Clk,
			 Enable =>Enable,
			 Reset => Reset,
			 Addr => Addr
			 );
 
    -- provide stimulus and check the result
    clk <= not clk after 50 ns;
    test: process
	variable vector : test_record_t;
	variable found_error : boolean := false;
    begin
	for i in test_patterns'range loop
	    vector := test_patterns(i);
            
	    -- apply the stimuls
	    Data_in <= vector.Data_in;
            Enable <= vector.Enable;
            Reset  <= vector.Reset;
            Addr   <= vector.Addr;
	    -- wait 1 clock cycle
	    wait for 100 ns;
          -- check the results
	   if (Data_out  /= vector.Data_out) then
		assert false
		    report "Data_out is " & to_string(Data_out)
		    & ". Expected " & to_string(vector.Data_out);
		found_error := true;
	    end if;
	end loop;

	assert not found_error
	  report "There were ERRORS in the test."
	  severity note;
	assert found_error
	  report "Test completed with no errors."
	  severity note;
	wait;
    end process;
end;



configuration test_shift_register_behavioural of testbench is
    for s_register
	for all: shift_register 
	    use entity work.shift_register(behavioural);
	end for;
    end for;
end test_shift_register_behavioural;

configuration test_shift_register_structural of testbench is
    for s_register
	for all: shift_register
	    use entity work.shift_register(Structural);
	end for;
    end for;
end test_shift_register_structural;