three_to_8_decoder.vhd

我是VHDL的初学者

library ieee;
use ieee.std_logic_1164.all;

Entity Decoder is 
       port (
       Dec_in: in bit_vector(2 downto 0);
       Dec_out: out bit_vector(7 downto 0)
       );
End Decoder;

Architecture Decoder1 of Decoder is
begin

process(Dec_in)

Begin
    Case Dec_in is 
         when "000"=>Dec_out<="11111110";
         when "001"=>Dec_out<="11111101";
         when "010"=>Dec_out<="11111011";
         when "011"=>Dec_out<="11110111";
         when "100"=>Dec_out<="11101111";
         when "101"=>Dec_out<="11011111";
         when "110"=>Dec_out<="10111111";
         when "111"=>Dec_out<="01111111";
         end case;
       
  end process;       
       
End Decoder1;