tlc.vhd

我是VHDL的初学者

library ieee;
use ieee.std_logic_1164.all;

Entity tlc is 
       port (
       
       Clk: in std_logic;
       sensor: in std_logic;
       rst: in std_logic
      
       );
End tlc;

Architecture tlc1 of tlc is
type state_type is (R,G,Y,L);
signal NS,EW: state_type;
signal state, next_state: integer range 1 to 12 ;
Begin
   process1: process(clk,rst,sensor)
   begin
              if ((clk'event) and (clk='1')) then
                if (rst='1') then
                   NS<=G;
                   EW<=R;
                else  
                   case state is 
                      when 1 to 4=>
                      NS<=G;EW<=R;next_state<=state+1;
                      when 5=>
                      NS<=Y;EW<=R;next_state<=6;
                      when 6 to 9=>
                      NS<=R;EW<=G;next_state<=state+1;
                      when 10=>
                     
                        if (sensor='1') then
                         NS<=R;EW<=G;
                        next_state<=11;
                        else 
                         NS<=R;EW<=G;
                        next_state<=1;
                        end if;
                      when 11=>
                      NS<=L;EW<=R;next_state<=12;
                      when 12=>
                      NS<=L;EW<=R;next_state<=1;
                    end case;
                 end if;
               end if;
            end process; 
   process2: process(clk)
   begin
                 if (clk'event and clk='1') then
                    state<=next_state;
                 end if;
             end process;
end Architecture tlc1;