pll1.v

ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.

// megafunction wizard: %ALTCLKLOCK%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclklock 

// ============================================================
// File Name: PLL1.v
// Megafunction Name(s):
// 			altclklock
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************


//Copyright (C) 1991-2000 Altera Corporation
//Any megafunction design, and related net list (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only to
//program PLD devices (but not masked PLD devices) from Altera.  Any other
//use of such megafunction design, net list, support information, device
//programming or simulation file, or any other related documentation or
//information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner.  Title to
//the intellectual property, including patents, copyrights, trademarks,
//trade secrets, or maskworks, embodied in any such megafunction design,
//net list, support information, device programming or simulation file, or
//any other related documentation or information provided by Altera or a
//megafunction partner, remains with Altera, the megafunction partner, or
//their respective licensors.  No other licenses, including any licenses
//needed under any third party's intellectual property, are provided herein.
`timescale 1 ps / 1 ps

module pll1 (
	inclock,
	locked,
	clock0,
	clock1);
/* synthesis black_box */
	input	  inclock;
	output	  locked;
	output	  clock0;
	output	  clock1;

/* synopsys translate_off */
	wire  sub_wire0;
	wire  sub_wire1;
	wire  sub_wire2;
	wire  clock0 = sub_wire0;
	wire  clock1 = sub_wire1;
	wire  locked = sub_wire2;

	altclklock	altclklock_component (
				.inclock (inclock),
				.clock0 (sub_wire0),
				.clock1 (sub_wire1),
				.locked (sub_wire2));
	defparam
		altclklock_component.inclock_period = 10000,
		altclklock_component.clock0_boost = 1,
		altclklock_component.clock1_boost = 2,
		altclklock_component.operation_mode = "NORMAL",
		altclklock_component.valid_lock_cycles = 5,
		altclklock_component.invalid_lock_cycles = 5,
		altclklock_component.valid_lock_multiplier = 5,
		altclklock_component.invalid_lock_multiplier = 5,
		altclklock_component.clock0_divide = 1,
		altclklock_component.clock1_divide = 1,
		altclklock_component.outclock_phase_shift = 0;

/* synopsys translate_on */
endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: DISPLAY_FREQUENCY STRING "25.0"
// Retrieval info: PRIVATE: USING_FREQUENCY NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "1"
// Retrieval info: PRIVATE: FEEDBACK_SOURCE NUMERIC "1"
// Retrieval info: PRIVATE: PHASE_UNIT NUMERIC "0"
// Retrieval info: PRIVATE: USING_PROGRAMMABLE_PHASE_SHIFT NUMERIC "1"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "40000"
// Retrieval info: CONSTANT: CLOCK0_BOOST NUMERIC "1"
// Retrieval info: CONSTANT: CLOCK1_BOOST NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: VALID_LOCK_CYCLES NUMERIC "5"
// Retrieval info: CONSTANT: INVALID_LOCK_CYCLES NUMERIC "5"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: CLOCK0_DIVIDE NUMERIC "1"
// Retrieval info: CONSTANT: CLOCK1_DIVIDE NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT NODEFVAL locked
// Retrieval info: USED_PORT: clock0 0 0 0 0 OUTPUT NODEFVAL clock0
// Retrieval info: USED_PORT: clock1 0 0 0 0 OUTPUT NODEFVAL clock1
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: clock0 0 0 0 0 @clock0 0 0 0 0
// Retrieval info: CONNECT: clock1 0 0 0 0 @clock1 0 0 0 0