test.bak

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   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Key3"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (300,340)
   VERTEXES ( (2,32) )
  }
  VTX  32, 0, 0
  {
   COORD (300,340)
  }
  TEXT  33, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (183,323,249,358)
   ALIGN 6
   MARGINS (1,1)
   PARENT 31
  }
  INSTANCE  34, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Key2"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (300,300)
   VERTEXES ( (2,35) )
  }
  VTX  35, 0, 0
  {
   COORD (300,300)
  }
  TEXT  36, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (183,283,249,318)
   ALIGN 6
   MARGINS (1,1)
   PARENT 34
  }
  INSTANCE  37, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Key1"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (300,260)
   VERTEXES ( (2,38) )
  }
  VTX  38, 0, 0
  {
   COORD (300,260)
  }
  TEXT  39, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (183,243,249,278)
   ALIGN 6
   MARGINS (1,1)
   PARENT 37
  }
  NET WIRE  40, 0, 0
  {
   VARIABLES
   {
    #NAME="SetCP"
   }
  }
  WIRE  41, 0, 0
  {
   NET 40
   VTX 95, 56
   VARIABLES
   {
    #NAMED="1"
   }
  }
  NET WIRE  43, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk4096Hz"
   }
  }
  WIRE  44, 0, 0
  {
   NET 43
   VTX 58, 92
   VARIABLES
   {
    #NAMED="1"
   }
  }
  NET WIRE  45, 0, 0
  {
   VARIABLES
   {
    #NAME="SetKey"
   }
  }
  WIRE  46, 0, 0
  {
   NET 45
   VTX 97, 52
   VARIABLES
   {
    #NAMED="1"
   }
  }
  INSTANCE  48, 0, 0
  {
   VARIABLES
   {
    #COMMENT="按键接口模块"
    #COMPONENT="KeyInterface"
    #LIBRARY="#default"
    #REFERENCE="U_KeyInterface"
    #SYMBOL="KeyInterface"
   }
   COORD (570,240)
   VERTEXES ( (6,50), (10,51), (14,53), (20,55), (28,58), (30,59), (32,60), (12,52), (18,54), (4,49), (24,56), (26,57), (8,189), (16,198) )
  }
  VTX  49, 0, 0
  {
   COORD (830,420)
  }
  VTX  50, 0, 0
  {
   COORD (570,260)
  }
  VTX  51, 0, 0
  {
   COORD (570,300)
  }
  VTX  52, 0, 0
  {
   COORD (830,340)
  }
  VTX  53, 0, 0
  {
   COORD (570,340)
  }
  VTX  54, 0, 0
  {
   COORD (830,380)
  }
  VTX  55, 0, 0
  {
   COORD (570,380)
  }
  VTX  56, 0, 0
  {
   COORD (830,460)
  }
  VTX  57, 0, 0
  {
   COORD (830,500)
  }
  VTX  58, 0, 0
  {
   COORD (570,420)
  }
  VTX  59, 0, 0
  {
   COORD (570,460)
  }
  VTX  60, 0, 0
  {
   COORD (570,500)
  }
  TEXT  61, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (570,184,769,219)
   ALIGN 8
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  62, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (570,600,732,635)
   MARGINS (1,1)
   PARENT 48
  }
  TEXT  63, 0, 0
  {
   TEXT "@COMMENT()"
   RECT (530,658,832,710)
   ALIGN 8
   MARGINS (1,1)
   PARENT 48
   FONT (18,0,0,400,0,1,0,"宋体")
  }
  NET WIRE  64, 0, 0
  WIRE  65, 0, 0
  {
   NET 64
   VTX 50, 38
  }
  NET WIRE  66, 0, 0
  WIRE  67, 0, 0
  {
   NET 66
   VTX 51, 35
  }
  NET WIRE  68, 0, 0
  WIRE  69, 0, 0
  {
   NET 68
   VTX 53, 32
  }
  TEXT  70, 0, 0
  {
   TEXT "$#NAME"
   RECT (451,431,589,460)
   ALIGN 9
   MARGINS (1,1)
   PARENT 71
  }
  WIRE  71, 0, 0
  {
   NET 87
   VTX 59, 91
   VARIABLES
   {
    #NAMED="1"
   }
  }
  TEXT  72, 0, 0
  {
   TEXT "$#NAME"
   RECT (838,341,1000,370)
   ALIGN 9
   MARGINS (1,1)
   PARENT 73
  }
  WIRE  73, 0, 0
  {
   NET 76
   VTX 96, 54
   VARIABLES
   {
    #NAMED="1"
   }
  }
  TEXT  74, 0, 0
  {
   TEXT "$#NAME"
   RECT (841,381,996,410)
   ALIGN 9
   MARGINS (1,1)
   PARENT 75
  }
  WIRE  75, 0, 0
  {
   NET 77
   VTX 98, 49
   VARIABLES
   {
    #NAMED="1"
   }
  }
  NET WIRE  76, 0, 0
  {
   VARIABLES
   {
    #NAME="StartPauseKey"
   }
  }
  NET WIRE  77, 0, 0
  {
   VARIABLES
   {
    #NAME="HoldResetKey"
   }
  }
  TEXT  78, 0, 0
  {
   TEXT "$#NAME"
   RECT (870,310,949,339)
   ALIGN 9
   MARGINS (1,1)
   PARENT 46
  }
  TEXT  79, 0, 0
  {
   TEXT "$#NAME"
   RECT (449,351,552,380)
   ALIGN 9
   MARGINS (1,1)
   PARENT 30
  }
  NET WIRE  80, 0, 0
  {
   VARIABLES
   {
    #NAME="IsFastAdjust"
   }
  }
  WIRE  81, 0, 0
  {
   NET 80
   VTX 94, 57
   VARIABLES
   {
    #NAMED="1"
   }
  }
  TEXT  83, 0, 0
  {
   TEXT "$#NAME"
   RECT (871,430,942,459)
   ALIGN 9
   MARGINS (1,1)
   PARENT 41
  }
  TEXT  84, 0, 0
  {
   TEXT "$#NAME"
   RECT (837,470,972,499)
   ALIGN 9
   MARGINS (1,1)
   PARENT 81
  }
  TEXT  85, 0, 0
  {
   TEXT "$#NAME"
   RECT (448,470,558,499)
   ALIGN 9
   MARGINS (1,1)
   PARENT 86
  }
  WIRE  86, 0, 0
  {
   NET 89
   VTX 88, 60
   VARIABLES
   {
    #NAMED="1"
   }
  }
  NET WIRE  87, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk100HzCE"
   }
  }
  VTX  88, 0, 0
  {
   COORD (450,500)
  }
  NET WIRE  89, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk8HzTC"
   }
  }
  VTX  90, 0, 0
  {
   COORD (460,380)
  }
  VTX  91, 0, 0
  {
   COORD (460,460)
  }
  VTX  92, 0, 0
  {
   COORD (460,420)
  }
  TEXT  93, 0, 0
  {
   TEXT "$#NAME"
   RECT (456,390,574,419)
   ALIGN 9
   MARGINS (1,1)
   PARENT 44
  }
  VTX  94, 0, 0
  {
   COORD (980,500)
  }
  VTX  95, 0, 0
  {
   COORD (980,460)
  }
  VTX  96, 0, 0
  {
   COORD (980,380)
  }
  VTX  97, 0, 0
  {
   COORD (980,340)
  }
  VTX  98, 0, 0
  {
   COORD (980,420)
  }
  INSTANCE  99, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="Input"
    #LIBRARY="#terminals"
    #REFERENCE="Clk2"
    #SYMBOL="Input"
    #VERILOG_TYPE="wire"
   }
   COORD (270,880)
   VERTEXES ( (2,158) )
  }
  TEXT  101, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (159,863,219,898)
   ALIGN 6
   MARGINS (1,1)
   PARENT 99
  }
  NET WIRE  102, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk8Hz"
   }
  }
  TEXT  104, 0, 0
  {
   TEXT "$#NAME"
   RECT (261,851,379,880)
   ALIGN 9
   MARGINS (1,1)
   PARENT 179
  }
  TEXT  106, 0, 0
  {
   TEXT "$#NAME"
   RECT (399,930,502,959)
   ALIGN 9
   MARGINS (1,1)
   PARENT 180
  }
  NET WIRE  108, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk1Hz"
   }
  }
  NET WIRE  110, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk2Hz"
   }
  }
  NET WIRE  112, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk1k"
   }
  }
  NET WIRE  114, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk512Hz"
   }
  }
  NET WIRE  116, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk4Hz"
   }
  }
  INSTANCE  118, 0, 0
  {
   VARIABLES
   {
    #COMPONENT="FrequenceDivde"
    #LIBRARY="#default"
    #REFERENCE="U1"
    #SYMBOL="FrequenceDivde"
   }
   COORD (560,860)
   VERTEXES ( (2,159), (6,161), (8,166), (18,168), (20,156), (16,171), (14,165), (10,162), (4,172), (24,176), (22,174) )
  }
  TEXT  130, 0, 0
  {
   TEXT "$#REFERENCE"
   RECT (560,804,599,839)
   ALIGN 8
   MARGINS (1,1)
   PARENT 118
  }
  TEXT  131, 0, 0
  {
   TEXT "$#COMPONENT"
   RECT (560,1240,774,1275)
   MARGINS (1,1)
   PARENT 118
  }
  TEXT  135, 0, 0
  {
   TEXT "$#NAME"
   RECT (889,850,951,879)
   ALIGN 9
   MARGINS (1,1)
   PARENT 183
  }
  TEXT  137, 0, 0
  {
   TEXT "$#NAME"
   RECT (868,890,973,919)
   ALIGN 9
   MARGINS (1,1)
   PARENT 184
  }
  TEXT  139, 0, 0
  {
   TEXT "$#NAME"
   RECT (881,930,960,959)
   ALIGN 9
   MARGINS (1,1)
   PARENT 178
  }
  TEXT  141, 0, 0
  {
   TEXT "$#NAME"
   RECT (881,1050,960,1079)
   ALIGN 9
   MARGINS (1,1)
   PARENT 181
  }
  TEXT  144, 0, 0
  {
   TEXT "$#NAME"
   RECT (851,1090,989,1119)
   ALIGN 9
   MARGINS (1,1)
   PARENT 186
  }
  NET WIRE  145, 0, 0
  {
   VARIABLES
   {
    #NAME="Clk1HzCE"
   }
  }
  TEXT  147, 0, 0
  {
   TEXT "$#NAME"
   RECT (864,1170,976,1199)
   ALIGN 9
   MARGINS (1,1)
   PARENT 187
  }
  TEXT  148, 0, 0
  {
   TEXT "$#NAME"
   RECT (895,970,974,999)
   ALIGN 9
   MARGINS (1,1)
   PARENT 185
  }
  TEXT  150, 0, 0
  {
   TEXT "$#NAME"
   RECT (876,1010,955,1039)
   ALIGN 9
   MARGINS (1,1)
   PARENT 182
  }
  TEXT  155, 0, 0
  {
   TEXT "$#NAME"
   RECT (865,1130,975,1159)
   ALIGN 9
   MARGINS (1,1)
   PARENT 188
  }
  VTX  156, 0, 0
  {
   COORD (840,960)
  }
  VTX  157, 0, 0
  {
   COORD (1000,960)
  }
  VTX  158, 0, 0
  {
   COORD (270,880)
  }
  VTX  159, 0, 0
  {
   COORD (560,880)
  }
  VTX  160, 0, 0
  {
   COORD (410,960)
  }
  VTX  161, 0, 0
  {
   COORD (560,960)
  }
  VTX  162, 0, 0
  {
   COORD (840,1080)
  }
  VTX  163, 0, 0
  {
   COORD (1000,1080)
  }
  VTX  164, 0, 0
  {
   COORD (990,1040)
  }
  VTX  165, 0, 0
  {
   COORD (840,1040)
  }
  VTX  166, 0, 0
  {
   COORD (840,880)
  }
  VTX  167, 0, 0
  {
   COORD (1000,880)
  }
  VTX  168, 0, 0
  {
   COORD (840,920)
  }
  VTX  169, 0, 0
  {
   COORD (1000,920)
  }
  VTX  170, 0, 0
  {
   COORD (1000,1000)
  }
  VTX  171, 0, 0
  {
   COORD (840,1000)
  }
  VTX  172, 0, 0
  {
   COORD (840,1120)
  }
  VTX  173, 0, 0
  {
   COORD (1000,1120)
  }
  VTX  174, 0, 0
  {
   COORD (840,1200)
  }
  VTX  175, 0, 0
  {
   COORD (1000,1200)
  }
  VTX  176, 0, 0
  {
   COORD (840,1160)
  }
  VTX  177, 0, 0
  {
   COORD (1000,1160)
  }
  WIRE  178, 0, 0
  {
   NET 102
   VTX 156, 157
   VARIABLES
   {
    #NAMED="1"
   }
  }
  WIRE  179, 0, 0
  {
   NET 43
   VTX 158, 159
   VARIABLES
   {
    #NAMED="1"
   }
  }
  WIRE  180, 0, 0
  {
   NET 29
   VTX 160, 161
   VARIABLES
   {