rssi_contr.v

来自「VerilogHDL.自动增益控制模块中产生控制电压的部分」· Verilog 代码 · 共 71 行

`timescale  1 ps / 1 ps
module RSSI_contr (data_in,clk,reset,d_out,rf,bb);

input  [9:0]data_in;
input  clk,
       reset;
output [9:0]d_out;
output [4:0]bb;
output [1:0]rf;
      
wire   [9:0]data_in;
wire   clk,         
       reset;       
wire   [9:0]d_out;
reg    [4:0]bb;
reg    [1:0]rf;
wire   [10:0]data_mod;
wire   [10:0]diff;
wire   pn,
       ran;

assign data_mod={1'b0,data_in[9:0]};
assign diff=data_mod-11'b00011111111;
assign ran=(diff[9:0]<=10)|(diff[9:0]>=1014);//range
assign pn=diff[10];//差的最高一位放进标志位pn里

always@(posedge clk)
  if(reset==1)
    begin
      rf<=2'b11;
      bb<=5'b11111;
    end
  else
    if(ran==1'b1)
      begin
        rf<=rf;
        bb<=bb;
      end
    else    
      case(pn)
        0:begin
            if(rf<2'b11)
            begin
              rf<=rf+1'b1;
              bb<=bb;
            end
          else
            begin
              rf<=rf;
              bb<=bb+1'b1;
            end
          end  
        1:begin
            if(bb>5'b0)
              begin
                rf<=rf;
                bb<=bb-1'b1;
              end
            else
              begin
                rf<=rf+2'b11;
                bb<=bb;
              end
          end
        default:begin
                  rf<=rf;
                  bb<=bb;
                end
      endcase              
assign d_out=data_in; 
endmodule