_primary.vhd

精通VerilogHDL：IC设计核心技术实例详解

library verilog;
use verilog.vl_types.all;
entity top is
    generic(
        row             : integer := 96;
        col             : integer := 96;
        rowsize         : integer := 7;
        col_size        : integer := 7;
        word_size       : integer := 16
    );
end top;