xljc.vhd

VHDL的序列检测源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xljc is
  PORT(qin,clk:in std_logic;
		   qout:out std_logic);
end entity xljc;

architecture behav of xljc is
   type states is(s0,s1,s2,s3,s4);
   signal current_state:states;

begin
  
process(clk)
  begin
	if (clk'event and clk='1') then
		case current_state is
		when s0=>if qin='1' then current_state<=s1;
                    else current_state<=s0;end if; qout<='0';
		when s1=>if qin='0' then current_state<=s2;
                    else current_state<=s1;end if; qout<='0';
		when s2=>if qin='0' then current_state<=s3;
                    else current_state<=s1;end if; qout<='0';
		when s3=>if qin='1' then current_state<=s4;qout<='1';
                    else current_state<=s0; qout<='0'; end if;
		when s4=>if qin='1' then current_state<=s1; 
                    else current_state<=s0;end if; qout<='0';
		when others=>current_state<=s0;
		end case;
	end if;
end process;

end architecture behav;