my_monitor_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    my_monitor_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec  3, 1998  12:23:34
Verilog_XL_Turbo_NT 2.6.9   Dec  3, 1998  12:23:34

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Compiling source file "my_monitor_test.v"
Highest level modules:
test


Adding monitors to all nets in module addbit:

At time 0.00:	 test.i1.a = 0
At time 0.00:	 test.i1.b = 0
At time 0.00:	 test.i1.ci = 0
At time 0.00:	 test.i1.n1 = 0
At time 0.00:	 test.i1.n2 = 0
At time 0.00:	 test.i1.n3 = 0
At time 0.00:	 test.i1.co = 0
At time 0.00:	 test.i1.sum = 0
At time 10.00:	 test.i1.a = 1
At time 10.00:	 test.i1.n1 = 1
At time 10.00:	 test.i1.sum = 1
At time 20.00:	 test.i1.a = 0
At time 20.00:	 test.i1.n1 = 0
At time 20.00:	 test.i1.sum = 0
At time 30.00:	 test.i1.b = 1
At time 30.00:	 test.i1.n1 = 1
At time 30.00:	 test.i1.sum = 1
At time 40.00:	 test.i1.a = 1
At time 40.00:	 test.i1.n2 = 1
At time 40.00:	 test.i1.n1 = 0
At time 40.00:	 test.i1.sum = 0
At time 40.00:	 test.i1.co = 1
L29 "my_monitor_test.v": $finish at simulation time 50
0 simulation events (use +profile or +listcounts option to count) + 22 accelerated events
CPU time: 0.7 secs to compile + 0.1 secs to link + 0.0 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec  3, 1998  12:23:35