my_monitor_test.v

来自「pli_handbook_examples_pc verilog hdl 与C」· Verilog 代码 · 共 52 行

/**********************************************************************
 * $my_monitor example -- Verilog HDL test bench.
 *
 * Verilog test bench to test the $my_monitor PLI application.
 *
 * For the book, "The Verilog PLI Handbook" by Stuart Sutherland
 *  Book copyright 1999, Kluwer Academic Publishers, Norwell, MA, USA
 *   Contact: www.wkap.il
 *  Example copyright 1998, Sutherland HDL Inc, Portland, Oregon, USA
 *   Contact: www.sutherland.com or [phone]
 *********************************************************************/
`timescale 1ns / 1ns
module test;
  reg   a, b, ci, clk;
  wire  sum, co;

  addbit i1 (a, b, ci, sum, co);

  initial
    $my_monitor(i1);
  
  initial
    begin
      a = 0; b = 0; ci = 0;
      #10 a = 1;
      #10 a = 0;
      #10 b = 1;
      #10 a = 1;
      #10 $finish;
    end

endmodule

/*** A gate level 1 bit adder model ***/
`timescale 1ns / 1ns
module addbit (a, b, ci, sum, co);
  input  a, b, ci;
  output sum, co;

  wire  a, b, ci, sum, co,
        n1, n2, n3;

  xor    (n1, a, b);
  xor    (sum, n1, ci);
  and    (n2, a, b);
  and    (n3, n1, ci);
  or     (co, n2, n3);

endmodule
/*********************************************************************/