exprinfo_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    exprinfo_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec 24, 1998  00:50:08
Verilog_XL_Turbo_NT 2.6.9   Dec 24, 1998  00:50:08

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Compiling source file "exprinfo_test.v"
Highest level modules:
test

Expression info:
 type = TF_STRING
 ngroups = 0
 vector size = 0
 sign = 0
 LHS select = 0
 RHS select = 0
 string value = Hello world


Expression info:
 type = TF_READWRITEREAL
 ngroups = 0
 vector size = 0
 sign = 1
 LHS select = 0
 RHS select = 0
 real value = 3.141500


Expression info:
 type = TF_READWRITE
 ngroups = 1
 vector size = 1
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = 0
  bvalbits[0] = 0


Expression info:
 type = TF_READWRITE
 ngroups = 1
 vector size = 32
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = f0f0f0f0
  bvalbits[0] = 0


Expression info:
 type = TF_READWRITE
 ngroups = 2
 vector size = 52
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = 55555555
  bvalbits[0] = 33333333
  avalbits[1] = 55555
  bvalbits[1] = 33333


Expression info:
 type = TF_RWBITSELECT
 ngroups = 1
 vector size = 1
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = 1
  bvalbits[0] = 0


Expression info:
 type = TF_RWPARTSELECT
 ngroups = 2
 vector size = 45
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = aaaaaaaa
  bvalbits[0] = 66666666
  avalbits[1] = aaa
  bvalbits[1] = 666


L34 "exprinfo_test.v": $finish at simulation time 8
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.6 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec 24, 1998  00:50:09