read_4state_value_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    read_4state_value_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec 23, 1998  23:44:43
Verilog_XL_Turbo_NT 2.6.9   Dec 23, 1998  23:44:43

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Compiling source file "read_4state_value_test.v"
Highest level modules:
test

Expression info:
 type = TF_STRING
 ngroups = 0
 vector size = 0
 sign = 0
 LHS select = 0
 RHS select = 0
 string value = Hello world


Expression info:
 type = TF_READWRITEREAL
 ngroups = 0
 vector size = 0
 sign = 1
 LHS select = 0
 RHS select = 0
 real value = 0.000000


Expression info:
 type = TF_READWRITE
 ngroups = 1
 vector size = 1
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = 1
  bvalbits[0] = 1


Expression info:
 type = TF_READWRITE
 ngroups = 1
 vector size = 32
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = ffffffff
  bvalbits[0] = ffffffff


Expression info:
 type = TF_READWRITE
 ngroups = 2
 vector size = 52
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = ffffffff
  bvalbits[0] = ffffffff
  avalbits[1] = fffff
  bvalbits[1] = fffff


Expression info:
 type = TF_RWBITSELECT
 ngroups = 1
 vector size = 1
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = 1
  bvalbits[0] = 1


Expression info:
 type = TF_RWPARTSELECT
 ngroups = 2
 vector size = 45
 sign = 0
 LHS select = 0
 RHS select = 0
 vector value (in hex):
  avalbits[0] = ffffffff
  bvalbits[0] = ffffffff
  avalbits[1] = 1fff
  bvalbits[1] = 1fff


 string value = Hello world

 real value = 0.000000

 vector value (in hex):
   avalbits[0] = 0
   bvalbits[0] = 0

 vector value (in hex):
   avalbits[0] = f0f0f0f0
   bvalbits[0] = 0

 vector value (in hex):
   avalbits[0] = 55555555
   bvalbits[0] = 33333333
   avalbits[1] = 55555
   bvalbits[1] = 33333

 vector value (in hex):
   avalbits[0] = 1
   bvalbits[0] = 0

 vector value (in hex):
   avalbits[0] = aaaaaaaa
   bvalbits[0] = 66666666
   avalbits[1] = aaa
   bvalbits[1] = 666

L34 "read_4state_value_test.v": $finish at simulation time 8
0 simulation events (use +profile or +listcounts option to count)
CPU time: 2.9 secs to compile + 1.2 secs to link + 0.4 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec 23, 1998  23:44:47