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📄 nodeinfo_test.log

📁 pli_handbook_examples_pc verilog hdl 与C的接口的典型例子
💻 LOG
字号:
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    nodeinfo_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec 24, 1998  16:51:49
Verilog_XL_Turbo_NT 2.6.9   Dec 24, 1998  16:51:49

Copyright (c) 1995 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995 UNIX Systems Laboratories, Inc.  Reproduced with Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-800-CADENC2 or send email to crc_customers@cadence.com

For more information on Cadence's Verilog-XL product line send email to
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Compiling source file "nodeinfo_test.v"
Highest level modules:
test

Reading Node Information
 node_symbol is reg1
 node_type = TF_REG_NODE
 node_ngroups = 1
 node_vec_size = 1
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 reg value (in hex):
   avalbits[0] = 1
   bvalbits[0] = 1

Reading Node Information
 node_symbol is reg2
 node_type = TF_REG_NODE
 node_ngroups = 2
 node_vec_size = 40
 node_sign = 0
 node_ms_index = 39
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 reg value (in hex):
   avalbits[0] = 55555555
   bvalbits[0] = 33333333
   avalbits[1] = 55
   bvalbits[1] = 33

Reading Node Information
 node_symbol is reg2
 node_type = TF_REG_NODE
 node_ngroups = 2
 node_vec_size = 40
 node_sign = 0
 node_ms_index = 39
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 reg value (in hex):
   avalbits[0] = 55555555
   bvalbits[0] = 33333333
   avalbits[1] = 55
   bvalbits[1] = 33

Reading Node Information
 node_symbol is int1
 node_type = TF_INTEGER_NODE
 node_ngroups = 1
 node_vec_size = 32
 node_sign = 1
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 integer value (in hex):
   avalbits[0] = 41424344
   bvalbits[0] = 0

Reading Node Information
 node_symbol is time1
 node_type = TF_TIME_NODE
 node_ngroups = 2
 node_vec_size = 64
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 time value (in hex):
   {avalbits[1],avalbits[0]} = 025
   {bvalbits[1],bvalbits[0]} = 00

Reading Node Information
 node_symbol is real1
 node_type = TF_REAL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 1
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 real value = 3.141500

Reading Node Information
 node_symbol is w1
 node_type = TF_NETSCALAR_NODE
 node_ngroups = 1
 node_vec_size = 1
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 scalar net value with strength (in hex):
   strength0 = 7f
   strength1 = f

Reading Node Information
 node_symbol is w2
 node_type = TF_NETVECTOR_NODE
 node_ngroups = 2
 node_vec_size = 40
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
   avalbits[0] = 55555555
   bvalbits[0] = 33333333
   avalbits[1] = 55
   bvalbits[1] = 33

Reading Node Information
 node_symbol is param1
 node_type = TF_REG_NODE
 node_ngroups = 1
 node_vec_size = 32
 node_sign = 1
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 reg value (in hex):
   avalbits[0] = 1
   bvalbits[0] = 0

Reading Node Information
 node_symbol is param2
 node_type = TF_REG_NODE
 node_ngroups = 1
 node_vec_size = 32
 node_sign = 1
 node_ms_index = 7
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 reg value (in hex):
   avalbits[0] = 2
   bvalbits[0] = 0

Reading Node Information
 node_symbol is param3
 node_type = TF_REG_NODE
 node_ngroups = 1
 node_vec_size = 32
 node_sign = 1
 node_ms_index = 47
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 reg value (in hex):
   avalbits[0] = 3
   bvalbits[0] = 0

Reading Node Information
 node_symbol is param4
 node_type = TF_REAL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 1
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0
 real value = 4.100000

Reading Node Information
 node_symbol is RAM
 node_type = TF_MEMORY_NODE
 node_ngroups = 3
 node_vec_size = 24
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 4
 node_lhs_element = 0
 node_rhs_element = 0
 memory arrays are not supported in this example

Reading Node Information
 node_symbol is ARRAY
 node_type = TF_MEMORY_NODE
 node_ngroups = 4
 node_vec_size = 32
 node_sign = 1
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 2
 node_lhs_element = 0
 node_rhs_element = 0
 memory arrays are not supported in this example

Reading Node Information
 node_symbol is (null)
 node_type = TF_NULL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0

Reading Node Information
 node_symbol is (null)
 node_type = TF_NULL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0

Reading Node Information
 node_symbol is (null)
 node_type = TF_NULL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0

Reading Node Information
 node_symbol is (null)
 node_type = TF_NULL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0

Reading Node Information
 node_symbol is (null)
 node_type = TF_NULL_NODE
 node_ngroups = 0
 node_vec_size = 0
 node_sign = 0
 node_ms_index = 0
 node_ls_index = 0
 node_mem_size = 0
 node_lhs_element = 0
 node_rhs_element = 0

L60 "nodeinfo_test.v": $finish at simulation time 20
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.7 secs to compile + 0.0 secs to link + 0.4 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec 24, 1998  16:51:50

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