port_info_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    port_info.v

Verilog_XL_Turbo_NT 2.6.9 log file created Nov 26, 1998  02:02:06
Verilog_XL_Turbo_NT 2.6.9   Nov 26, 1998  02:02:06

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Compiling source file "port_info.v"
Highest level modules:
test


Module addbit (instance test.i1)
  Port name is a
    Size is 1
    Direction is input
    Low conn data type is vpiNet
    High conn data type is vpiReg
  Port name is b
    Size is 1
    Direction is input
    Low conn data type is vpiNet
    High conn data type is vpiReg
  Port name is ci
    Size is 1
    Direction is input
    Low conn data type is vpiNet
    High conn data type is vpiReg
  Port name is sum
    Size is 1
    Direction is output
    Low conn data type is vpiNet
    High conn data type is vpiNet
  Port name is co
    Size is 1
    Direction is output
    Low conn data type is vpiNet
    High conn data type is vpiNet
L20 "port_info.v": $finish at simulation time 2
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.6 secs to compile + 0.1 secs to link + 0.0 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Nov 26, 1998  02:02:07