cf_interleaver_12_32.py

interleaver即交织器

    found = 0
    for bit in range(11, -1, -1):
      if found:
        if self.n5 & (2L ** bit):
          self.sim_file.write("1")
        else:
          self.sim_file.write("0")
      else:
        if self.n5 & (2L ** bit):
          self.sim_file.write("b1")
          found = 1
    if not found:
      self.sim_file.write("b0")
    self.sim_file.write(" #\n")
    found = 0
    for bit in range(31, -1, -1):
      if found:
        if self.n6 & (2L ** bit):
          self.sim_file.write("1")
        else:
          self.sim_file.write("0")
      else:
        if self.n6 & (2L ** bit):
          self.sim_file.write("b1")
          found = 1
    if not found:
      self.sim_file.write("b0")
    self.sim_file.write(" $\n")
    if self.n80:
      self.sim_file.write("1%\n")
    else:
      self.sim_file.write("0%\n")
    if self.n81:
      self.sim_file.write("1&\n")
    else:
      self.sim_file.write("0&\n")
    found = 0
    for bit in range(31, -1, -1):
      if found:
        if self.n82 & (2L ** bit):
          self.sim_file.write("1")
        else:
          self.sim_file.write("0")
      else:
        if self.n82 & (2L ** bit):
          self.sim_file.write("b1")
          found = 1
    if not found:
      self.sim_file.write("b0")
    self.sim_file.write(" '\n")
    self.sim_file.write("$end\n")

  def sim_end(self):
    self.sim_file.write("#%d\n" % self.sim_count)
    self.sim_file.close()

  def sim_sample(self):
    changed = 0
    if self.sim_n3 != self.n3:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n3:
        self.sim_file.write("1!\n")
      else:
        self.sim_file.write("0!\n")
      self.sim_n3 = self.n3
    if self.sim_n4 != self.n4:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n4:
        self.sim_file.write("1\"\n")
      else:
        self.sim_file.write("0\"\n")
      self.sim_n4 = self.n4
    if self.sim_n5 != self.n5:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      found = 0
      for bit in range(11, -1, -1):
        if found:
          if self.n5 & (2L ** bit):
            self.sim_file.write("1")
          else:
            self.sim_file.write("0")
        else:
          if self.n5 & (2L ** bit):
            self.sim_file.write("b1")
            found = 1
      if not found:
        self.sim_file.write("b0")
      self.sim_file.write(" #\n")
      self.sim_n5 = self.n5
    if self.sim_n6 != self.n6:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      found = 0
      for bit in range(31, -1, -1):
        if found:
          if self.n6 & (2L ** bit):
            self.sim_file.write("1")
          else:
            self.sim_file.write("0")
        else:
          if self.n6 & (2L ** bit):
            self.sim_file.write("b1")
            found = 1
      if not found:
        self.sim_file.write("b0")
      self.sim_file.write(" $\n")
      self.sim_n6 = self.n6
    if self.sim_n80 != self.n80:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n80:
        self.sim_file.write("1%\n")
      else:
        self.sim_file.write("0%\n")
      self.sim_n80 = self.n80
    if self.sim_n81 != self.n81:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n81:
        self.sim_file.write("1&\n")
      else:
        self.sim_file.write("0&\n")
      self.sim_n81 = self.n81
    if self.sim_n82 != self.n82:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      found = 0
      for bit in range(31, -1, -1):
        if found:
          if self.n82 & (2L ** bit):
            self.sim_file.write("1")
          else:
            self.sim_file.write("0")
        else:
          if self.n82 & (2L ** bit):
            self.sim_file.write("b1")
            found = 1
      if not found:
        self.sim_file.write("b0")
      self.sim_file.write(" '\n")
      self.sim_n82 = self.n82
    self.sim_count = self.sim_count + 1