cf_interleaver_12_32.py

interleaver即交织器

    self.n27 = 0x0L
    self.n26 = 0x0L
    self.n25 = 0x0L
    self.n22 = 0x1L
    self.n21 = 0x2L
    self.n20 = 0x0L
    self.n19 = 0x0L
    self.n18 = 0x1L
    self.n17 = 0x1L
    self.n16 = 0x0L
    self.n7 = 0x001L
    self.n6 = data_i
    self.n5 = addr_i
    self.n4 = write_i
    self.n3 = swap_i
    self.n2 = 0x0L
    self.n1 = 0x1L
    data_o = self.n79
    self.n82 = self.n79
    if self.n15 == self.n58:
      self.n59 = 1L
    else:
      self.n59 = 0L
    self.n57r = self.n2
    self.n57e = self.n1
    self.n57d = self.n3
    self.n32 = self.n3 << 1 | self.n43
    self.n10 = (self.n15 + self.n7) & 0xFFFL
    sync_secondary_o = self.n59
    self.n81 = self.n59
    if self.n32 == self.n28:
      self.n45 = 1L
    else:
      self.n45 = 0L
    if self.n32 == self.n27:
      self.n44 = 1L
    else:
      self.n44 = 0L
    if self.n32 == self.n22:
      self.n35 = 1L
    else:
      self.n35 = 0L
    if self.n32 == self.n21:
      self.n34 = 1L
    else:
      self.n34 = 0L
    if self.n32 == self.n20:
      self.n33 = 1L
    else:
      self.n33 = 0L
    self.n15r = self.n3
    self.n15e = self.n1
    self.n15d = self.n10
    if self.n45:
      self.n48 = self.n25
    else:
      self.n48 = self.n84
    if self.n35:
      self.n36 = self.n17
    else:
      self.n36 = self.n16
    if self.n44:
      self.n49 = self.n26
    else:
      self.n49 = self.n48
    if self.n34:
      self.n37 = self.n18
    else:
      self.n37 = self.n36
    self.n66 = self.n4 & self.n49
    self.n50 = ~self.n49 & 0x1L
    if self.n33:
      self.n38 = self.n19
    else:
      self.n38 = self.n37
    self.n78r = self.n2
    self.n78e = self.n1
    self.n78d = self.n50
    self.n71e = self.n1
    self.n71w = self.n66
    self.n71aw = self.n5
    self.n71ar = self.n15
    self.n71dw = self.n6
    self.n60 = self.n4 & self.n50
    self.n43r = self.n2
    self.n43e = self.n1
    self.n43d = self.n38
    self.n65e = self.n1
    self.n65w = self.n60
    self.n65aw = self.n5
    self.n65ar = self.n15
    self.n65dw = self.n6
    return (sync_primary_o, sync_secondary_o, data_o, )

  def cycle_clock(self):
    if self.n15r:
      self.n15 = 0L
    elif self.n15e:
        self.n15 = self.n15d
    if self.n43r:
      self.n43 = 0L
    elif self.n43e:
        self.n43 = self.n43d
    if self.n57r:
      self.n57 = 0L
    elif self.n57e:
        self.n57 = self.n57d
    if self.n65e:
      if self.n65w:
        self.n65m[self.n65aw] = self.n65dw
      self.n65 = self.n65m[self.n65ar]
    if self.n71e:
      if self.n71w:
        self.n71m[self.n71aw] = self.n71dw
      self.n71 = self.n71m[self.n71ar]
    if self.n78r:
      self.n78 = 0L
    elif self.n78e:
        self.n78 = self.n78d

  def sim_init(self, vcdFile):
    self.sim_file = open(vcdFile, 'w')
    self.sim_count = 1
    self.init()
    self.sim_n3 = self.n3
    self.sim_n4 = self.n4
    self.sim_n5 = self.n5
    self.sim_n6 = self.n6
    self.sim_n80 = self.n80
    self.sim_n81 = self.n81
    self.sim_n82 = self.n82
    self.sim_file.write("$date\n")
    self.sim_file.write("  " + time.strftime("%a %b %d %H:%M:%S %Y", time.localtime()) + "\n")
    self.sim_file.write("$end\n")
    self.sim_file.write("$version\n  Confluence 0.6.3 -- Launchbird Design Systems, Inc.\n$end\n")
    self.sim_file.write("$timescale\n  1 ns\n$end\n")
    self.sim_file.write("$scope module cf_interleaver_12_32 $end\n")
    self.sim_file.write("$var wire 1 ! swap_i $end\n")
    self.sim_file.write("$var wire 1 \" write_i $end\n")
    self.sim_file.write("$var wire 12 # addr_i $end\n")
    self.sim_file.write("$var wire 32 $ data_i $end\n")
    self.sim_file.write("$var wire 1 % sync_primary_o $end\n")
    self.sim_file.write("$var wire 1 & sync_secondary_o $end\n")
    self.sim_file.write("$var wire 32 ' data_o $end\n")
    self.sim_file.write("$upscope $end\n")
    self.sim_file.write("$enddefinitions $end\n")
    self.sim_file.write("#0\n")
    self.sim_file.write("$dumpvars\n")
    if self.n3:
      self.sim_file.write("1!\n")
    else:
      self.sim_file.write("0!\n")
    if self.n4:
      self.sim_file.write("1\"\n")
    else:
      self.sim_file.write("0\"\n")