cf_interleaver_9_64.py

interleaver即交织器

    self.n78d = self.n50
    self.n71e = self.n1
    self.n71w = self.n66
    self.n71aw = self.n5
    self.n71ar = self.n15
    self.n71dw = self.n6
    self.n60 = self.n4 & self.n50
    self.n43r = self.n2
    self.n43e = self.n1
    self.n43d = self.n38
    self.n65e = self.n1
    self.n65w = self.n60
    self.n65aw = self.n5
    self.n65ar = self.n15
    self.n65dw = self.n6
    return (sync_primary_o, sync_secondary_o, data_o, )

  def cycle_clock(self):
    if self.n15r:
      self.n15 = 0L
    elif self.n15e:
        self.n15 = self.n15d
    if self.n43r:
      self.n43 = 0L
    elif self.n43e:
        self.n43 = self.n43d
    if self.n57r:
      self.n57 = 0L
    elif self.n57e:
        self.n57 = self.n57d
    if self.n65e:
      if self.n65w:
        self.n65m[self.n65aw] = self.n65dw
      self.n65 = self.n65m[self.n65ar]
    if self.n71e:
      if self.n71w:
        self.n71m[self.n71aw] = self.n71dw
      self.n71 = self.n71m[self.n71ar]
    if self.n78r:
      self.n78 = 0L
    elif self.n78e:
        self.n78 = self.n78d

  def sim_init(self, vcdFile):
    self.sim_file = open(vcdFile, 'w')
    self.sim_count = 1
    self.init()
    self.sim_n3 = self.n3
    self.sim_n4 = self.n4
    self.sim_n5 = self.n5
    self.sim_n6 = self.n6
    self.sim_n80 = self.n80
    self.sim_n81 = self.n81
    self.sim_n82 = self.n82
    self.sim_file.write("$date\n")
    self.sim_file.write("  " + time.strftime("%a %b %d %H:%M:%S %Y", time.localtime()) + "\n")
    self.sim_file.write("$end\n")
    self.sim_file.write("$version\n  Confluence 0.6.3 -- Launchbird Design Systems, Inc.\n$end\n")
    self.sim_file.write("$timescale\n  1 ns\n$end\n")
    self.sim_file.write("$scope module cf_interleaver_9_64 $end\n")
    self.sim_file.write("$var wire 1 ! swap_i $end\n")
    self.sim_file.write("$var wire 1 \" write_i $end\n")
    self.sim_file.write("$var wire 9 # addr_i $end\n")
    self.sim_file.write("$var wire 64 $ data_i $end\n")
    self.sim_file.write("$var wire 1 % sync_primary_o $end\n")
    self.sim_file.write("$var wire 1 & sync_secondary_o $end\n")
    self.sim_file.write("$var wire 64 ' data_o $end\n")
    self.sim_file.write("$upscope $end\n")
    self.sim_file.write("$enddefinitions $end\n")
    self.sim_file.write("#0\n")
    self.sim_file.write("$dumpvars\n")
    if self.n3:
      self.sim_file.write("1!\n")
    else:
      self.sim_file.write("0!\n")
    if self.n4:
      self.sim_file.write("1\"\n")
    else:
      self.sim_file.write("0\"\n")
    found = 0
    for bit in range(8, -1, -1):
      if found:
        if self.n5 & (2L ** bit):
          self.sim_file.write("1")
        else:
          self.sim_file.write("0")
      else:
        if self.n5 & (2L ** bit):
          self.sim_file.write("b1")
          found = 1
    if not found:
      self.sim_file.write("b0")
    self.sim_file.write(" #\n")
    found = 0
    for bit in range(63, -1, -1):
      if found:
        if self.n6 & (2L ** bit):
          self.sim_file.write("1")
        else:
          self.sim_file.write("0")
      else:
        if self.n6 & (2L ** bit):
          self.sim_file.write("b1")
          found = 1
    if not found:
      self.sim_file.write("b0")
    self.sim_file.write(" $\n")
    if self.n80:
      self.sim_file.write("1%\n")
    else:
      self.sim_file.write("0%\n")
    if self.n81:
      self.sim_file.write("1&\n")
    else:
      self.sim_file.write("0&\n")
    found = 0
    for bit in range(63, -1, -1):
      if found:
        if self.n82 & (2L ** bit):
          self.sim_file.write("1")
        else:
          self.sim_file.write("0")
      else:
        if self.n82 & (2L ** bit):
          self.sim_file.write("b1")
          found = 1
    if not found:
      self.sim_file.write("b0")
    self.sim_file.write(" '\n")
    self.sim_file.write("$end\n")

  def sim_end(self):
    self.sim_file.write("#%d\n" % self.sim_count)
    self.sim_file.close()

  def sim_sample(self):
    changed = 0
    if self.sim_n3 != self.n3:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n3:
        self.sim_file.write("1!\n")
      else:
        self.sim_file.write("0!\n")
      self.sim_n3 = self.n3
    if self.sim_n4 != self.n4:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n4:
        self.sim_file.write("1\"\n")
      else:
        self.sim_file.write("0\"\n")
      self.sim_n4 = self.n4
    if self.sim_n5 != self.n5:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      found = 0
      for bit in range(8, -1, -1):
        if found:
          if self.n5 & (2L ** bit):
            self.sim_file.write("1")
          else:
            self.sim_file.write("0")
        else:
          if self.n5 & (2L ** bit):
            self.sim_file.write("b1")
            found = 1
      if not found:
        self.sim_file.write("b0")
      self.sim_file.write(" #\n")
      self.sim_n5 = self.n5
    if self.sim_n6 != self.n6:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      found = 0
      for bit in range(63, -1, -1):
        if found:
          if self.n6 & (2L ** bit):
            self.sim_file.write("1")
          else:
            self.sim_file.write("0")
        else:
          if self.n6 & (2L ** bit):
            self.sim_file.write("b1")
            found = 1
      if not found:
        self.sim_file.write("b0")
      self.sim_file.write(" $\n")
      self.sim_n6 = self.n6
    if self.sim_n80 != self.n80:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n80:
        self.sim_file.write("1%\n")
      else:
        self.sim_file.write("0%\n")
      self.sim_n80 = self.n80
    if self.sim_n81 != self.n81:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      if self.n81:
        self.sim_file.write("1&\n")
      else:
        self.sim_file.write("0&\n")
      self.sim_n81 = self.n81
    if self.sim_n82 != self.n82:
      if not changed:
        changed = 1
        self.sim_file.write("#%d\n" % self.sim_count)
      found = 0
      for bit in range(63, -1, -1):
        if found:
          if self.n82 & (2L ** bit):
            self.sim_file.write("1")
          else:
            self.sim_file.write("0")
        else:
          if self.n82 & (2L ** bit):
            self.sim_file.write("b1")
            found = 1
      if not found:
        self.sim_file.write("b0")
      self.sim_file.write(" '\n")
      self.sim_n82 = self.n82
    self.sim_count = self.sim_count + 1