cf_interleaver_8_8.v

interleaver即交织器

//
//  Copyright (c) 2003 Launchbird Design Systems, Inc.
//  All rights reserved.
//  
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
//    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//  
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//  
//  
//  Overview:
//  
//    Memory interleavers are often used in DSP for reordering continuous streaming data.
//    The interleaver is comprised of two interleaving memories.  One memory loads and
//    reorders data, while the other memory dumps the data to the output.
//    Once loading and dumping of data are complete, the memories reverse roles.
//    The dumping memory continuously cycles though the entire memory starting at address 0.
//  
//  Interface:
//  
//    Synchronization:
//      clock_c  : Clock input.
//  
//    Inputs:
//      swap_i   : Swap signal to interleave memories.  Pulse occurs one frame before the switch
//                 and may coincide with the last input data.
//      write_i  : Write enable for input data.
//      addr_i   : Address for input data.
//      data_i   : Input data.
//  
//    Outputs:
//      sync_primary_o    : Output sync plus occurs one frame before data new dump.
//      sync_secondary_o  : Secondary sync plus occurs one frame before data at address 0 is dumped.
//      data_o            : Output data.
//  
//  Built In Parameters:
//  
//    Address Width  = 8
//    Data Width     = 8
//  
//  
//  
//  
//  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com
//  
//  Build Date : Fri Aug 22 09:32:55 CDT 2003
//  
//  Interface
//  
//    Build Name    : cf_interleaver_8_8
//    Clock Domains : clock_c  
//    Vector Input  : swap_i(1)
//    Vector Input  : write_i(1)
//    Vector Input  : addr_i(8)
//    Vector Input  : data_i(8)
//    Vector Output : sync_primary_o(1)
//    Vector Output : sync_secondary_o(1)
//    Vector Output : data_o(8)
//  
//  
//  

`timescale 1 ns / 1 ns

module cf_interleaver_8_8 (clock_c, swap_i, write_i, addr_i, data_i, sync_primary_o, sync_secondary_o, data_o);
input  clock_c;
input  swap_i;
input  write_i;
input  [7:0] addr_i;
input  [7:0] data_i;
output sync_primary_o;
output sync_secondary_o;
output [7:0] data_o;
wire   n1;
wire   n2;
wire   [7:0] n3;
cf_interleaver_8_8_1 s1 (clock_c, swap_i, write_i, addr_i, data_i, n1, n2, n3);
assign sync_primary_o = n1;
assign sync_secondary_o = n2;
assign data_o = n3;
endmodule

module cf_interleaver_8_8_1 (clock_c, i1, i2, i3, i4, o1, o2, o3);
input  clock_c;
input  i1;
input  i2;
input  [7:0] i3;
input  [7:0] i4;
output o1;
output o2;
output [7:0] o3;
wire   n1;
wire   n2;
wire   s3_1;
wire   s3_2;
wire   [7:0] s3_3;
assign n1 = 1'b1;
assign n2 = 1'b0;
cf_interleaver_8_8_2 s3 (clock_c, n1, n2, i1, i2, i3, i4, s3_1, s3_2, s3_3);
assign o3 = s3_3;
assign o2 = s3_2;
assign o1 = s3_1;
endmodule

module cf_interleaver_8_8_2 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2, o3);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  [7:0] i5;
input  [7:0] i6;
output o1;
output o2;
output [7:0] o3;
wire   [7:0] n1;
wire   [7:0] n2;
reg    [7:0] n3;
wire   n4;
reg    n5;
wire   [7:0] n6;
wire   n7;
wire   n8;
wire   [7:0] n9;
reg    [7:0] n9a;
reg    [7:0] n9m [255:0];
wire   n10;
wire   [7:0] n11;
reg    [7:0] n11a;
reg    [7:0] n11m [255:0];
reg    n12;
wire   [7:0] n13;
wire   s14_1;
assign n1 = 8'b00000001;
assign n2 = n3 + n1;
initial n3 = 8'b00000000;
always @ (posedge clock_c)
  if (i3 == 1'b1)
    n3 <= 8'b00000000;
  else if (i1 == 1'b1)
    n3 <= n2;
assign n4 = ~s14_1;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i3;
assign n6 = 8'b00000000;
assign n7 = n3 == n6;
assign n8 = i4 & n4;
initial n9a = 8'b00000000;
always @ (posedge clock_c)
  if (i1 == 1'b1) begin
    if (n8 == 1'b1)
      n9m[i5] <= i6;
    n9a <= n3;
  end
assign n9 = n9m[n9a];
assign n10 = i4 & s14_1;
initial n11a = 8'b00000000;
always @ (posedge clock_c)
  if (i1 == 1'b1) begin
    if (n10 == 1'b1)
      n11m[i5] <= i6;
    n11a <= n3;
  end
assign n11 = n11m[n11a];
initial n12 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n12 <= 1'b0;
  else if (i1 == 1'b1)
    n12 <= n4;
assign n13 = n12 ? n11 : n9;
cf_interleaver_8_8_3 s14 (clock_c, i1, i2, i3, s14_1);
assign o3 = n13;
assign o2 = n7;
assign o1 = n5;
endmodule

module cf_interleaver_8_8_3 (clock_c, i1, i2, i3, o1);
input  clock_c;
input  i1;
input  i2;
input  i3;
output o1;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [1:0] n5;
reg    n6;
wire   s7_1;
wire   s8_1;
assign n1 = 1'b0;
assign n2 = 1'b1;
assign n3 = 1'b1;
assign n4 = 1'b0;
assign n5 = {i3, n6};
initial n6 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 1'b0;
  else if (i1 == 1'b1)
    n6 <= s7_1;
cf_interleaver_8_8_5 s7 (n1, n2, n3, n4, n5, s7_1);
cf_interleaver_8_8_4 s8 (n5, s8_1);
assign o1 = s8_1;
endmodule

module cf_interleaver_8_8_4 (i1, o1);
input  [1:0] i1;
output o1;
wire   n1;
wire   n2;
wire   [1:0] n3;
wire   [1:0] n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
assign n1 = 1'b0;
assign n2 = 1'b0;
assign n3 = 2'b00;
assign n4 = 2'b10;
assign n5 = i1 == n3;
assign n6 = i1 == n4;
assign n7 = n6 ? n1 : n9;
assign n8 = n5 ? n2 : n7;
assign n9 = 1'b1;
assign o1 = n8;
endmodule

module cf_interleaver_8_8_5 (i1, i2, i3, i4, i5, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  [1:0] i5;
output o1;
wire   [1:0] n1;
wire   [1:0] n2;
wire   [1:0] n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
assign n1 = 2'b00;
assign n2 = 2'b10;
assign n3 = 2'b01;
assign n4 = i5 == n1;
assign n5 = i5 == n2;
assign n6 = i5 == n3;
assign n7 = n6 ? i2 : i1;
assign n8 = n5 ? i3 : n7;
assign n9 = n4 ? i4 : n8;
assign o1 = n9;
endmodule