📄 dct8_final.txt
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-- DO NOT use WORD WRAP to view properly
-- IDCT-M is a medium speed 1D IDCT core
-- it can accept a continous stream of 12-bit input words at a rate of
-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video
-- the core is 100% synthesizable
--
-- Designed by Sherif Taher Eid, sherif_taher@ieee.org
--
-- Top entity is DCT8_final
--
-- ENTITY DCT8_final IS
-- PORT(
-- bit_in_even : IN std_logic ;
-- bit_in_odd : IN std_logic ;
-- clk : IN std_ulogic ;
-- reset_int : IN std_ulogic ;
-- indicate : OUT std_logic_vector (3 DOWNTO 0) ;
-- minus_out : OUT unsigned (11 DOWNTO 0) ;
-- plus_out : OUT unsigned (11 DOWNTO 0)
-- );
--
-- The core is used for IDCT calculation
-- input words are assumed to be of 12 bits length
-- for a certain input vector
--
-- I = [I0 I1 I2 I3 I4 I5 I6 I7]
--
-- an output vector is created which is the 1D IDCT of I
--
-- x = [x0 x1 x2 x3 x4 x5 x6 x7]
--
-- there are two single bit inputs "bit_in_even" and "bit_in_odd"
--
-- knowing that every input word is composed of 12 bits
--
-- e.g. I1[11 downto 0], I1[0] is the LSB
--
-- when inputing a certain word to the core start with the LSB
--
-- time (ck cycles): 0 1 2 3 ............. 12 ........
--
-- input : I1[0] I1[1] I1[2] .......... I1[11] ....
--
-- input to the core is as follows
--
-- time (ck cycles): 0 12 24 36 48 60 72 84
--
-- bit_in_even : I0... I2... I4... I6... input the next 4 even words
--
-- bit_in_odd : I1... I3....I5... I7... input the next 4 odd words
--
-- assert the intial LSB bits at the first rising edge after asserting
-- "reset" to '0'. "reset" is active '1'
--
-- output comes out in the form of parallel 12-bit words, the "indicate"
--
-- vector is a 4-bit output showing proper instances and orders of the output words as follows
--
--
-- indicate (stable value at ck rising_edge) : 0001 0010 0100 1000
--
-- plus_out : x0 x1 x2 x3
--
-- minus_out : x7 x6 x5 x4
--
-- any further inquiries please contact sherif_taher@ieee.org
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY add12signed IS
PORT(
a : IN unsigned (11 DOWNTO 0) ;
b : IN unsigned (11 DOWNTO 0) ;
output : OUT unsigned (12 DOWNTO 0)
);
-- Declarations
END add12signed ;
ARCHITECTURE beh OF add12signed IS
signal outtemp : signed(12 downto 0);
BEGIN
outtemp <= signed(a(11)&a) + signed(b(11)&b);
output <= unsigned(outtemp);
END beh;
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY add14signed IS
PORT(
ain : IN unsigned (13 DOWNTO 0) ;
bin : IN unsigned (13 DOWNTO 0) ;
output : OUT unsigned (13 DOWNTO 0)
);
-- Declarations
END add14signed ;
--
--
ARCHITECTURE beh OF add14signed IS
signal outtemp : signed(13 downto 0);
BEGIN
outtemp <= signed(ain) + signed(bin);
output <= unsigned(outtemp);
END beh;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY controller IS
PORT(
clk : IN std_ulogic ;
reset : IN std_ulogic ;
clk1 : OUT std_ulogic ;
clk2 : OUT std_ulogic ;
compl : OUT std_ulogic ;
enable0 : OUT std_ulogic ;
enable1 : OUT std_ulogic ;
address : BUFFER unsigned (1 DOWNTO 0)
);
-- Declarations
END controller ;
--
--
ARCHITECTURE beh OF controller IS
BEGIN
main : process(clk)
variable count : integer := 0;
variable state : integer range 1 to 20 := 19;
begin
if rising_edge(clk) then
if (reset = '1')then
clk1 <= '0';
clk2 <= '0';
enable0 <= '0';
enable1 <= '0';
compl <= '0';
address <= "00";
count := 0;
state := 1;
else
case state is
when 1 =>
enable0 <= '1';
enable1 <= '1';
state := 2;
when 2 =>
state := 3;
when 3 =>
state := 4;
when 4 =>
state := 5;
when 5 =>
state := 6;
when 6 =>
state := 7;
when 7 =>
state := 8;
when 8 =>
state := 9;
when 9 =>
state := 10;
when 10 =>
state := 11;
when 11 =>
state := 12;
when 12 =>
compl <= '1';
state := 13;
when 13 =>
compl <= '0';
state := 14;
when 14 =>
state := 20;
when 20 =>
clk1 <= '1';
enable0 <= '0';
address <= address + "01";
count := count + 1;
state := 15;
when 15 =>
clk1 <= '0';
enable0 <= '1';
state := 16;
when 16 =>
if count = 4 then
clk2 <= '1';
state := 19;
else
state := 17;
end if;
when 17 =>
state := 18;
when 18 =>
state := 2;
enable0 <= '1';
enable1 <= '1';
when 19 =>
clk1 <= '0';
clk2 <= '0';
enable0 <= '0';
enable1 <= '0';
compl <= '0';
address <= "00";
count := 0;
state := 1;
end case;
end if;
end if;
end process main;
END beh;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY delay_e IS
PORT(
clk : IN std_ulogic ;
d_in : IN unsigned (6 DOWNTO 0) ;
enable_rom : IN std_ulogic ;
reset : IN std_ulogic ;
address_out : OUT unsigned (1 DOWNTO 0) ;
clk1out : OUT std_ulogic ;
clk2out : OUT std_ulogic ;
compl_out : OUT std_ulogic ;
d_out : OUT unsigned (6 DOWNTO 0) ;
enable_1_out : OUT std_ulogic ;
enable_out : OUT std_ulogic ;
enable_rom_out : OUT std_ulogic ;
reset_out : OUT std_ulogic
);
-- Declarations
END delay_e ;
--
--
ARCHITECTURE beha OF delay_e IS
signal d_int : unsigned(6 downto 0);
signal enable_rom_int : std_ulogic;
BEGIN
reset_out <= reset;
process(clk,reset)
begin
if reset = '0' then
d_int <= "0000000";
enable_rom_int <= '0';
d_out <= "0000000";
address_out <= "00";
clk1out <= '0';
clk2out <= '0';
compl_out <= '0';
enable_out <= '0';
enable_1_out <= '0';
enable_rom_out <= '0';
else
if rising_edge(clk) then
d_int <= d_in;
enable_rom_int <= enable_rom;
d_out <= d_int;
address_out <= d_int(6 downto 5);
clk1out <= d_int(4);
clk2out <= d_int(3);
compl_out <= d_int(2);
enable_out <= d_int(1);
enable_1_out <= d_int(0);
enable_rom_out <= enable_rom_int;
end if;
end if;
end process;
END beha;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY div2 IS
PORT(
Sin : IN unsigned (12 downto 0) ;
Sout : OUT unsigned (11 downto 0)
);
-- Declarations
END div2 ;
--
--
ARCHITECTURE arch OF div2 IS
BEGIN
Sout <= Sin(12 downto 1);
END arch;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mux_adder IS
PORT(
clk : IN std_ulogic ;
dbus00 : IN unsigned (13 DOWNTO 0) ;
dbus01 : IN unsigned (13 DOWNTO 0) ;
dbus02 : IN unsigned (13 DOWNTO 0) ;
dbus03 : IN unsigned (13 DOWNTO 0) ;
dbuse0 : IN unsigned (13 DOWNTO 0) ;
dbuse1 : IN unsigned (13 DOWNTO 0) ;
dbuse2 : IN unsigned (13 DOWNTO 0) ;
dbuse3 : IN unsigned (13 DOWNTO 0) ;
reset_int : IN std_ulogic ;
sig00 : IN std_ulogic ;
sig01 : IN std_ulogic ;
sig02 : IN std_ulogic ;
sig03 : IN std_ulogic ;
indicate : OUT std_logic_vector (3 DOWNTO 0) ;
minus : OUT unsigned (12 DOWNTO 0) ;
plus : OUT unsigned (12 DOWNTO 0)
);
-- Declarations
END mux_adder ;
--
--
ARCHITECTURE behavioral OF mux_adder IS
signal x00,x01,x02,x03,xe0,xe1,xe2,xe3 : unsigned(12 downto 0);
signal plustmp,minustmp : unsigned(12 downto 0);
--signal sig00_d,sig01_d,sig02_d,sig03_d : std_ulogic;
BEGIN
-- concurrent signal assignments
x00 <= dbus00(13)&dbus00(13 downto 2);
x01 <= dbus01(13)&dbus01(13 downto 2);
x02 <= dbus02(13)&dbus02(13 downto 2);
x03 <= dbus03(13)&dbus03(13 downto 2);
xe0 <= dbuse0(13)&dbuse0(13 downto 2);
xe1 <= dbuse1(13)&dbuse1(13 downto 2);
xe2 <= dbuse2(13)&dbuse2(13 downto 2);
xe3 <= dbuse3(13)&dbuse3(13 downto 2);
--plus <= unsigned(plustmp);
--minus <= unsigned(minustmp);
plus <= plustmp;
minus <= minustmp;
process(reset_int,clk)
begin
if reset_int = '1' then
plustmp <= "0000000000000";
minustmp <= "0000000000000";
indicate <= "0000";
else
if rising_edge(clk) then
if sig00 = '1' then
plustmp <= x00 + xe0;
minustmp <= x00 - xe0;
indicate <= "0001";
elsif sig01 = '1' then
plustmp <= x01 + xe1;
minustmp <= x01 - xe1;
indicate <= "0010";
elsif sig02 = '1' then
plustmp <= x02 + xe2;
minustmp <= x02 - xe2;
indicate <= "0100";
elsif sig03 = '1' then
plustmp <= x03 + xe3;
minustmp <= x03 - xe3;
indicate <= "1000";
else
indicate <= "0000";
end if;
end if;
end if;
end process;
END behavioral;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY reg12b IS
PORT(
ain : IN unsigned (11 DOWNTO 0) ;
clk : IN std_ulogic ;
enable : IN std_ulogic ;
aout : OUT unsigned (11 DOWNTO 0)
);
-- Declarations
END reg12b ;
--
--
ARCHITECTURE beh OF reg12b IS
BEGIN
process(clk,enable)
begin
if enable = '0' then
aout <= "000000000000";
else
if rising_edge(clk) then
aout <= ain;
end if;
end if;
end process;
END beh;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY reg13b IS
PORT(
ain : IN unsigned (12 DOWNTO 0) ;
clk : IN std_ulogic ;
enable : IN std_ulogic ;
aout : OUT unsigned (12 DOWNTO 0)
);
-- Declarations
END reg13b ;
--
--
ARCHITECTURE beh OF reg13b IS
BEGIN
process(clk,enable)
begin
if enable = '0' then
aout <= "0000000000000";
else
if rising_edge(clk) then
aout <= ain;
end if;
end if;
end process;
END beh;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY reg14b IS
PORT(
ain : IN unsigned (13 DOWNTO 0) ;
clk : IN std_ulogic ;
enable : IN std_ulogic ;
aout : OUT unsigned (13 DOWNTO 0)
);
-- Declarations
END reg14b ;
--
--
ARCHITECTURE beh OF reg14b IS
BEGIN
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