_primary.vhd

来自「８＊８的乘法器verilog源代码,经过编译仿真的」· VHDL 代码 · 共 8 行

library verilog;
use verilog.vl_types.all;
entity lpm_multest is
    generic(
        dely            : integer := 25
    );
end lpm_multest;