_primary.vhd

８＊８的乘法器verilog源代码,经过编译仿真的

library verilog;
use verilog.vl_types.all;
entity lpm_mult is
    generic(
        lpm_type        : string  := "lpm_mult";
        lpm_widtha      : integer := 8;
        lpm_widthb      : integer := 8;
        lpm_widths      : integer := 8;
        lpm_widthp      : integer := 16;
        lpm_representation: string  := "UNSIGNED";
        lpm_pipeline    : integer := 0;
        lpm_hint        : string  := "UNUSED"
    );
    port(
        result          : out    vl_logic_vector;
        dataa           : in     vl_logic_vector;
        datab           : in     vl_logic_vector;
        sum             : in     vl_logic_vector;
        clock           : in     vl_logic;
        clken           : in     vl_logic;
        aclr            : in     vl_logic
    );
end lpm_mult;