vga_register_bank.vhd

Avalon_VGA

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY vga_register_bank IS 
PORT (
	resetn			: IN std_logic;
	clk			: IN std_logic;
	chipselect		: IN std_logic;
	address			: IN std_logic_vector(2 downto 0);
	read			: IN std_logic;
	set_picture_end_irq	: IN std_logic;
	irq			: OUT std_logic;
	readdata		: OUT std_logic_vector(31 downto 0);
	write			: IN std_logic;
	writedata		: IN std_logic_vector(31 downto 0);
	image_address		: OUT std_logic_vector(31 downto 0);
	size			: OUT std_logic_vector(31 downto 0);
	control			: OUT std_logic_vector(31 downto 0)
);
END vga_register_bank;

ARCHITECTURE rtl OF vga_register_bank IS

-- registers
	SIGNAL image_address_reg: std_logic_vector(31 downto 0);
	SIGNAL size_reg		: std_logic_vector(31 downto 0);
	SIGNAL control_reg	: std_logic_vector(31 downto 0);
	SIGNAL status_reg	: std_logic_vector(1 downto 0);
BEGIN

register_bank: PROCESS(clk,resetn)
BEGIN
	IF resetn = '0' THEN
		size_reg <= (others => '0');
		control_reg <= (others => '0');
	ELSIF rising_edge(clk) THEN
		IF chipselect = '1' THEN
			IF write = '1' THEN
				CASE address IS
					WHEN "000" =>
						image_address_reg <= writedata;
					WHEN "001" => 
						size_reg <= writedata;
					WHEN "010" =>
						control_reg <= writedata;
					WHEN others =>
						null;
				END CASE;
			END IF;
			IF read = '1' THEN
				CASE address IS
					WHEN "000" =>
						readdata <= image_address_reg;
					WHEN "001" => 
						readdata <= size_reg;
					WHEN "010" =>
						readdata <= control_reg;
					WHEN "011" =>
						readdata(31 downto 2) <= (others => '0');
						readdata(1 downto 0) <= status_reg;
					WHEN others =>
						readdata <= (others => '0');
				END CASE;
			ELSE
				readdata <= (others => '0');
			END IF;
		ELSE
			readdata <= (others => '0');
		END IF;
	END IF;
END PROCESS;

image_address <= image_address_reg;
size <= size_reg;
control <= control_reg;

-- clear the irq on any write to the control register bank
irq_control: PROCESS(clk,resetn)
BEGIN
	IF resetn = '0' THEN
		irq <= '0';
		status_reg <= (others => '0');
	ELSIF rising_edge(clk) THEN
		IF set_picture_end_irq = '1' THEN
			irq <= '1';
			status_reg(0) <= set_picture_end_irq;
		ELSIF chipselect = '1' AND write = '1' THEN
			irq <= '0';
			status_reg <= (others => '0');
		END IF;
	END IF;
END PROCESS;

END rtl;